- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄375989 > FW82371 (Intel Corp.) PCI-TO-ISA / IDE XCELERATOR PIIX4 PDF資料下載
參數(shù)資料
| 型號(hào)： | FW82371 |
| 廠商： | Intel Corp. |
| 英文描述： | PCI-TO-ISA / IDE XCELERATOR PIIX4 |
| 中文描述： | PCI到的ISA / IDE的XCELERATOR PIIX4 |
| 文件頁(yè)數(shù)： | 159/284頁(yè) |
| 文件大?。?/td> | 1042K |
| 代理商： | FW82371 |
第1頁(yè)第2頁(yè)第3頁(yè)第4頁(yè)第5頁(yè)第6頁(yè)第7頁(yè)第8頁(yè)第9頁(yè)第10頁(yè)第11頁(yè)第12頁(yè)第13頁(yè)第14頁(yè)第15頁(yè)第16頁(yè)第17頁(yè)第18頁(yè)第19頁(yè)第20頁(yè)第21頁(yè)第22頁(yè)第23頁(yè)第24頁(yè)第25頁(yè)第26頁(yè)第27頁(yè)第28頁(yè)第29頁(yè)第30頁(yè)第31頁(yè)第32頁(yè)第33頁(yè)第34頁(yè)第35頁(yè)第36頁(yè)第37頁(yè)第38頁(yè)第39頁(yè)第40頁(yè)第41頁(yè)第42頁(yè)第43頁(yè)第44頁(yè)第45頁(yè)第46頁(yè)第47頁(yè)第48頁(yè)第49頁(yè)第50頁(yè)第51頁(yè)第52頁(yè)第53頁(yè)第54頁(yè)第55頁(yè)第56頁(yè)第57頁(yè)第58頁(yè)第59頁(yè)第60頁(yè)第61頁(yè)第62頁(yè)第63頁(yè)第64頁(yè)第65頁(yè)第66頁(yè)第67頁(yè)第68頁(yè)第69頁(yè)第70頁(yè)第71頁(yè)第72頁(yè)第73頁(yè)第74頁(yè)第75頁(yè)第76頁(yè)第77頁(yè)第78頁(yè)第79頁(yè)第80頁(yè)第81頁(yè)第82頁(yè)第83頁(yè)第84頁(yè)第85頁(yè)第86頁(yè)第87頁(yè)第88頁(yè)第89頁(yè)第90頁(yè)第91頁(yè)第92頁(yè)第93頁(yè)第94頁(yè)第95頁(yè)第96頁(yè)第97頁(yè)第98頁(yè)第99頁(yè)第100頁(yè)第101頁(yè)第102頁(yè)第103頁(yè)第104頁(yè)第105頁(yè)第106頁(yè)第107頁(yè)第108頁(yè)第109頁(yè)第110頁(yè)第111頁(yè)第112頁(yè)第113頁(yè)第114頁(yè)第115頁(yè)第116頁(yè)第117頁(yè)第118頁(yè)第119頁(yè)第120頁(yè)第121頁(yè)第122頁(yè)第123頁(yè)第124頁(yè)第125頁(yè)第126頁(yè)第127頁(yè)第128頁(yè)第129頁(yè)第130頁(yè)第131頁(yè)第132頁(yè)第133頁(yè)第134頁(yè)第135頁(yè)第136頁(yè)第137頁(yè)第138頁(yè)第139頁(yè)第140頁(yè)第141頁(yè)第142頁(yè)第143頁(yè)第144頁(yè)第145頁(yè)第146頁(yè)第147頁(yè)第148頁(yè)第149頁(yè)第150頁(yè)第151頁(yè)第152頁(yè)第153頁(yè)第154頁(yè)第155頁(yè)第156頁(yè)第157頁(yè)第158頁(yè)當(dāng)前第159頁(yè)第160頁(yè)第161頁(yè)第162頁(yè)第163頁(yè)第164頁(yè)第165頁(yè)第166頁(yè)第167頁(yè)第168頁(yè)第169頁(yè)第170頁(yè)第171頁(yè)第172頁(yè)第173頁(yè)第174頁(yè)第175頁(yè)第176頁(yè)第177頁(yè)第178頁(yè)第179頁(yè)第180頁(yè)第181頁(yè)第182頁(yè)第183頁(yè)第184頁(yè)第185頁(yè)第186頁(yè)第187頁(yè)第188頁(yè)第189頁(yè)第190頁(yè)第191頁(yè)第192頁(yè)第193頁(yè)第194頁(yè)第195頁(yè)第196頁(yè)第197頁(yè)第198頁(yè)第199頁(yè)第200頁(yè)第201頁(yè)第202頁(yè)第203頁(yè)第204頁(yè)第205頁(yè)第206頁(yè)第207頁(yè)第208頁(yè)第209頁(yè)第210頁(yè)第211頁(yè)第212頁(yè)第213頁(yè)第214頁(yè)第215頁(yè)第216頁(yè)第217頁(yè)第218頁(yè)第219頁(yè)第220頁(yè)第221頁(yè)第222頁(yè)第223頁(yè)第224頁(yè)第225頁(yè)第226頁(yè)第227頁(yè)第228頁(yè)第229頁(yè)第230頁(yè)第231頁(yè)第232頁(yè)第233頁(yè)第234頁(yè)第235頁(yè)第236頁(yè)第237頁(yè)第238頁(yè)第239頁(yè)第240頁(yè)第241頁(yè)第242頁(yè)第243頁(yè)第244頁(yè)第245頁(yè)第246頁(yè)第247頁(yè)第248頁(yè)第249頁(yè)第250頁(yè)第251頁(yè)第252頁(yè)第253頁(yè)第254頁(yè)第255頁(yè)第256頁(yè)第257頁(yè)第258頁(yè)第259頁(yè)第260頁(yè)第261頁(yè)第262頁(yè)第263頁(yè)第264頁(yè)第265頁(yè)第266頁(yè)第267頁(yè)第268頁(yè)第269頁(yè)第270頁(yè)第271頁(yè)第272頁(yè)第273頁(yè)第274頁(yè)第275頁(yè)第276頁(yè)第277頁(yè)第278頁(yè)第279頁(yè)第280頁(yè)第281頁(yè)第282頁(yè)第283頁(yè)第284頁(yè)
E
Each DMA channel is hardwired to the compatible settings for DMA device size: channels [3:0] are hardwired to
8-bit, count-by-bytes transfers, and channels [7:5] are hardwired to 16-bit, count-by-words (address shifted)
transfers. PIIX4 provides the timing control and data size translation necessary for the DMA transfer between the
memory (ISA or DRAM) and the ISA Bus IO. ISA-Compatible and Type F-DMA timing is supported.
82371AB (PIIX4)
159
4/9/97 2:23 PM PIIX4aDS
INTEL CONFIDENTIAL
(until publication date)
PRELIMINARY
PIIX4 provides 24-bit addressing in compliance with the ISA-Compatible specification. Each channel includes a
16-bit ISA-Compatible Current Register which holds the 16 least-significant bits of the 24-bit address, an ISA-
Compatible Page Register which contains the eight next most significant bits of address.
The DMA controller also features refresh address generation, and autoinitialization following a DMA termination.
The DMA controller is at any time either in master mode or slave mode. In master mode, the DMA controller is
either servicing a DMA slave’s request for DMA cycles, or allowing a 16-bit ISA master to use the bus via a
cascaded DREQ signal. In slave mode, PIIX4 monitors both the ISA Bus and PCI, decoding and responding to
I/O read and write commands that address its registers.
Note that a DMA device (I/O device) is always on the ISA Bus, but the memory referenced is located on either
an ISA Bus device or on PCI. When PIIX4 is running a compatible DMA cycle, it drives the MEMR# or MEMW#
strobes if the address is less than 16 Mbytes (000000h–FFFFFFh). These memory strobes are generated
regardless of whether the cycle is decoded for PCI or ISA memory. The SMEMR# and SMEMW# are generated
if the address is less than 1 Mbytes (0000000h–00FFFFFh). If the address is greater than
16 Mbytes (1000000h–7FFFFFFh), the MEMR# or MEMW# strobe are not generated to avoid aliasing issues.
NOTE
BIOS Programming:
For type F timing mode DMA transfers, the channel must be programmed with a
memory range that will be forwarded to PCI. This means that if BIOS detects that ISA memory is used in
the system (i.e., that the top of memory reported to the OS is higher than the top of memory programmed
in PIIX4 Top of Memory register), the BIOS should not enable type F for any channel.
PIIX4 drives the AEN signal asserted (high) during DMA cycles to prevent the I/O devices from misinterpreting
the DMA cycle as a valid I/O cycle. The BALE signal is also driven high during DMA cycles.
8.4.1.
DMA TRANSFER MODES
The channels can be programmed for any of four transfer modes. The transfer modes include single, block,
demand, or cascade. Each of the three active transfer modes (single, block, and demand), can perform three
different types of transfers (read, write, or verify). Note that memory-to-memory transfers are not supported by
PIIX4.
Single Transfer Mode
In single transfer mode, the DMA is programmed to make one transfer only. The byte/word count is decremented
and the address decremented or incremented following each transfer. When the byte/word count “rolls over”
from zero to FFFFh, a Terminal Count (TC) causes an autoinitialize if the channel has been programmed to do
so.
To be recognized DREQ must be held active until DACK# becomes active. If DREQ is held active throughout
the single transfer, the bus is released after a single transfer. With DREQ asserted high, the DMA I/O device re-
arbitrate for the bus. Upon winning the bus, another single transfer is performed. This allows other ISA bus
masters a chance to acquire the bus.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| FW82801E | Intel 82801E Communications I/O Controller Hub (C-ICH) |
| FWB150 | 1.5 AMP FAST RECOVERY BRIDGE RECTIFIERS |
| FWB151 | 1.5 AMP FAST RECOVERY BRIDGE RECTIFIERS |
| FWB1510 | 1.5 AMP FAST RECOVERY BRIDGE RECTIFIERS |
| FWB152 | 1.5 AMP FAST RECOVERY BRIDGE RECTIFIERS |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| FW82371EB | 制造商:Intel 功能描述:IC INTEL 82371EB 352BGA 制造商:Rochester Electronics LLC 功能描述: |
| FW82371EB S L37M | 制造商:Intel 功能描述:Embedded Processor 352-Pin BGA |
| FW82371EB SL37M | 制造商:Intel 功能描述: |
| FW82371MB | 制造商:Rochester Electronics LLC 功能描述:PCI-ISA BRIDGE, T&R, SPEC SL3CG - Bulk |
| FW82439HX | 制造商:Intel 功能描述: |
發(fā)布緊急采購(gòu)，3分鐘左右您將得到回復(fù)。