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82371AB (PIIX4)
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4/9/97 2:23 PM PIIX4aDS
INTEL CONFIDENTIAL
(until publication date)
PRELIMINARY
Global Release:
[BIOS_EN]
[BIOS_STS]
— Writes to the Power Management 1 Control Register (PM1_CNTRL) with bit 2 set will
generate an SMI# if enabled. See the “Peripheral Device Management” section for more
information.
Thermal Alarm (THRM# Assertion):
[THRM_EN]
[THRM_STS]
—
Polarity Select:
[THRM_POL]
— The THRM# signal will set the [THRM_STS] bit when asserted and if enabled will generate
an SMI#. The assertion polarity can be controlled to allow system code to detect when
THRM# signal transitions from low to high or high to low. This signal can also be used to
generate an SCI. When asserted, the THRM# will also cause automatic clock throttling (see
the “Clock Control” section for additional details).
11.5.3.
GLOBAL STANDBY TIMER OPERATION
The Global Standby Timer is used to monitor for global system activity during normal operation and can be
reloaded by system activity events. When enabled, the timer loads and starts counting down. Enabled system
events cause the timer to reload its initial value and begin counting down again. If no system events reload the
timer, it will eventually count to zero. Upon this expiration, it generates an SMI#. When the system is placed in a
Suspend Mode, the Global Standby Timer can also be used to generate a resume event.
The global standby timer stops counting when the SM_FREEZE bit is set. This can be used to keep it from
counting down when the system is executing an SMI routine. The SM_FREEZE bit is disregarded while in a
Suspend state, so that the Global Standby Timer counts down independent of SM_FREEZE value.
Global Standby Timer Programming Information:
Resolution: 32 second or 4 minute
Count: 7
bit
Count and SMI# Enable:
Expiration Status:
[GSTBY_SEL]
[GSTBY_CNT]
[GSTBY_EN]
[GSTBY_STS]
Global Standby Timer Reload Events
IRQ1, IRQ12/M:
NMI, INIT, IRQ[1,3:7,9:15]:
Device 0–13 Monitors:
Video Monitor (PCI Bus Utilization):
PCI Bus Master Activity:
[GRLD_EN_KBC_MS]
[GRLD_EN_IRQ]
[GRLD_EN_DEVx] x=0–13
[VIDEO_EN]
[BM_RLD_DEV8]
[GRLD_EN_DEV8]