82371AB (PIIX4)
E
54
4/9/97 2:23 PM PIIX4aDS
INTEL CONFIDENTIAL
(until publication date)
PRELIMINARY
4.1.3.
PCICMD—PCI COMMAND REGISTER (FUNCTION 0)
Address Offset:
Default Value:
Attribute:
04–05h
0007h
Read/Write
This 16-bit register provides basic control over the PIIX4’s ability to respond to PCI cycles.
Bit
Description
15:10
Reserved.
Read as 0.
9
Fast Back-to-Back Enable (Not Implemented).
This bit is hardwired to 0.
8
SERR# Enable (SERRE).
1=Enable. 0=Disable. When enabled (and DLC Register, bit 3=1),
a delayed transaction time-out causes PIIX4 to assert the SERR# signal. The PCISTS register
reports the status of the SERR# signal.
7
Address and Data Stepping Enable (Not Implemented).
The PIIX4 does not support address and
data stepping. This bit is hardwired to 0.
6
Parity Error Detect Enable (Not Implemented).
PIIX4 does not support parity error detection. This
bit is hardwired to 0.
5
VGA Palette Snoop Enable (Not Implemented).
PIIX4 does not support VGA palette snooping.
This bit is hardwired to 0.
4
Memory Write and Invalidate Enable (Not Implemented).
PIIX4 does not generate Memory Write
and Invalidate PCI transactions. This bit is hardwired to 0.
3
Special Cycle Enable (SCE)
. 1=Enable, PIIX4 recognizes all PCI shutdown special cycles.
0=Disable, PIIX4 ignores all PCI Special Cycles.
2
Bus Master Enable (Not Implemented).
PIIX4 does not support disabling its function 0 bus master
capability. This bit is hardwired to 1.
1
Memory Access (Not Implemented).
PIIX4 does not support disabling function 0 access to
memory. This bit is hardwired to 1.
0
I/O Space Access Enable (Not Implemented).
PIIX4 does not support disabling its function 0
response to PCI I/O cycles. This bit is hardwired to 1.