82371AB (PIIX4)
E
62
4/9/97 2:23 PM PIIX4aDS
INTEL CONFIDENTIAL
(until publication date)
PRELIMINARY
4.1.15.
APICBASE—APIC BASE ADDRESS RELOCATION REGISTER (FUNCTION 0)
Address Offset:
Default Value:
Attribute:
80h
00h
Read/Write
This register provides the modifier for the APIC base address. APIC is mapped in the memory space at the
locations FEC0_xy00h and FEC0_xy10h (x=0–Fh, y=0,4,8,Ch). The value of ‘y’ is defined by bits [1,0] and the
value of ‘x’ is defined by bits [5:2]. Thus, the relocation register provides 1-Kbyte address granularity (i.e.
potentially up to 64 I/O APICs can be uniformly addresses in the memory space). The default value of 00h
provides mapping of the I/O APIC unit at the addresses FEC0_0000h and FEC0_0010h.
Bit
Description
7
Reserved.
6
A12 Mask.
This bit determines selects whether APICCS# is generated for one or two I/O APIC
address ranges. When bit 6=1, address bit 12 is ignored allowing the APICCS# signal to be
generated for two consecutive I/O APIC address ranges. External logic is needed to select individual
I/O APICs by combining SA12 and APICCS#. For example, when bit 6=1 (and x and y=0), APICCS#
is generated for addresses FEC0_0000h, FEC0_0010, as well as FEC0_1000h, FEC0_1010. When
bit 6=0, APICCS# is generated for one I/O APIC address range.
5:2
X-Base Address.
Bits[5:2] are compared with PCI address bits AD[15:12], respectively.
1:0
Y-Base Address.
Bits[1:0] are compared with PCI address bits AD[11:10], respectively.
4.1.16.
DLC—DETERMINISTIC LATENCY CONTROL REGISTER (FUNCTION 0)
Address Offset:
Default Value:
Attribute:
82h
00h
Read/Write
This register enables and disables the Delayed Transaction and Passive Release functions. When enabled,
these functions make PIIX4 PCI revision 2.1 compliant.
The 2.1 revision of the PCI specification requires much tighter controls on target and master latency. Targets
must respond with TRDY# or STOP# within 16 clocks of FRAME#, and masters must assert IRDY# within
8 PCI clocks for any data phase. PCI cycles to or from ISA typically take longer than this. PIIX4
provides a
programmable delayed completion
mechanism described in the PCI specification to meet the required target
latencies. This includes a Discard Timer which times out if a PCI Master with an outstanding delayed transaction
has not retried the transaction for greater than 2
PCI clocks.
ISA bridges also support Guaranteed Access Time (GAT) mode, which will now violate the spirit of the PCI
specification. PIIX4
provides a programmable passive release
mechanism to meet the required master latencies.
When passive release is enabled in PIIX4,
ISA masters may see long delays in accesses to any PCI memory,
including the main DRAM array. The ISA GAT mode is not supported with passive release enabled.
ISA masters
must
honor IOCHRDY.