E
82371AB (PIIX4)
63
4/9/97 2:23 PM PIIX4aDS
INTEL CONFIDENTIAL
(until publication date)
PRELIMINARY
Bit
Description
7:4
Reserved.
3
SERR# Generation Enable (Due To Delayed Transaction Time-out).
1=Enable. 0=Disable.
2
USB Passive Release Enable (USBPR).
1=Enable. 0=Disable. When enabled, this allows PIIX4 to
use Passive Release while transferring control information or data for USB transactions. When
disabled, PIIX4 will perform PCI accesses for USB without using Passive Release.
1
Passive Release Enable.
1=Enable the Passive Release mechanism encoded on the PHOLD#
signal when PIIX4 is a PCI Master. 0=Disable Passive Release.
0
Delayed Transaction Enable.
1=Enable the Delayed Transaction mechanism when PIIX4 is the
target of a PCI transaction. 0=Disable Delayed Transaction mechanism.
4.1.17.
PDMACFG—PCI DMA CONFIGURATION REGISTER (FUNCTION 0)
Address Offset:
Default Value:
Attribute:
90–91h
0000h
Read/Write
This register defines the type of DMA performed by a particular DMA channel. If a channel is programmed for
Distributed DMA mode, PIIX4 does not respond to either the ISA DREQ signal or to the PC/PCI encoding for that
channel.
Bit
Description
15:14
DMA CH 7 Select.
These bits define the type of DMA performed on this channel.
Bits[15:14]
DMA Type
00
Normal ISA DMA (default)
01
PC/PCI DMA
10
Distributed DMA
11
Reserved
13:12
DMA CH 6 Select.
This field define the type of DMA performed on this channel.
Bits[13:12]
DMA Type
00
Normal ISA DMA (default)
01
PC/PCI DMA
10
Distributed DMA
11
Reserved
11:10
DMA CH 5 Select.
These bits define the type of DMA performed on this channel.
Bits[11:10]
DMA Type
00
Normal ISA DMA (default)
01
PC/PCI DMA
10
Distributed DMA
11
Reserved
9:8
Reserved.