82371AB (PIIX4)
E
222
4/9/97 2:23 PM PIIX4aDS
INTEL CONFIDENTIAL
(until publication date)
PRELIMINARY
11.3.5.9.
Device 8:
LPT (Parallel Port)
Device 8 monitors accesses to Parallel Port or GPI17.
It can also be used to monitor for PCI Bus
Master activity (PIIX4 or any other PCI Master).
Device 8 System Events:
— PCI accesses to IO addresses for a parallel port, selectable below.
This can cause idle,
burst, or global standby
timer reloads,
IO trap SMI#, or forwarding of the cycle from PCI
to ISA.
— DACKx# assertion (x=0,1,3) if enabled (see below).
This can
cause
idle, burst, and
global standby timer reloads.
— Assertion of GPI17.
The polarity of active signal (high or low) is selectable.
This can
cause idle, burst,
or global standby timer reloads.
— Assertion of PCIREQ[0:3] or PHOLD#, signifying PCI Master activity. This can cause
idle, burst,
or global standby timer reloads or IO trap SMI#.
The Bus Master activity can
be programmed to cause a Trap SMI# independently of IO address accesses.
Device 8 Address Ranges:
LPT (Parallel Port):
378
–
37Fh, 778–77Ah
or
278
–
27Fh, 678
–
67Ah
or
3BC
–
3BFh, 7BC
–
7BEh
[LPT_MON_EN]
[LPT_DEC_SEL]
Device 8 Idle Timer:
Resolution: 1 msec or 1 sec
Count: 5
bit
GPI Enable:
GPI Polarity Select:
DACKx# Enables:
DACKx# Select (DACKx#=0,1,3):
Device 8 ISA Forwarding Enable:
Device 8 Idle Timer Reload:
Global Standby Timer Reload:
Burst Timer Reload (Fast Burst Only):
Decode, DACK GPI:
Above and Bus Master:
Bus Master Only:
Idle Timer Expiration SMI#:
Trap SMI# (LPT or GPI only):
Trap SMI# (Bus Master only):
[IDL_SEL_DEV8]
[BM_CNT]
[GPI_EN_DEV8]
[GPI_POL_DEV8]
[RES_EN_DEV8]
[LPT_DMA_SEL]
[EIO_EN_DEV8]
[IDL_EN_DEV8]
[GRLD_EN_DEV8]
[BRLD_EN_DEV8]
[BM_RLD_DEV8]
[BRLD_EN_BM]
[IDL_EN_DEV8]
[IDL_STS_DEV8]
[TRP_EN_DEV8]
[TRP_STS_DEV8]
[BM_TRP_EN]
[BM_STS]