
TSE Transmission Switch Element Datasheet
Released
Proprietary and Confidential to PMC-Sierra, Inc., and for its Customers’ Internal Use
Document ID: PMC-1991258, Issue 7
10
List of Figures
Figure 1 Representative TSE Application.........................................................................18
Figure 2 Fabric with One Plane of Depth One..................................................................19
Figure 3 Fabric with Two Planes of Depth One................................................................20
Figure 4 Fabric with Four Planes of Depth One. ..............................................................20
Figure 5 Fabric with One Plane of Depth Three and Height Thirty-Two...........................21
Figure 6 Fabric with One Plane of Depth Three and Height Sixty-Four ...........................22
Figure 7 Generic LVDS Link Block Diagram.....................................................................45
Figure 8 Input Observation Cell (IN_CELL)....................................................................124
Figure 9 Output Cell (OUT_CELL)..................................................................................124
Figure 10 Bidirectional Cell (IO_CELL)...........................................................................125
Figure 11 Layout of Output Enable and Bidirectional Cells............................................125
Figure 12 Boundary Scan Architecture...........................................................................130
Figure 13 TAP Controller Finite State Machine ..............................................................132
Figure 14 “J0” Synchronization Control ..........................................................................141
Figure 15 Fabric Components ........................................................................................143
Figure 16 LOAD:LOAD Null Fabrics...............................................................................144
Figure 17 TBS Fabrics (non-redundant).........................................................................145
Figure 18 TSE Fabric (redundant)..................................................................................146
Figure 19 TSE Fabric with Differing Path Lengths..........................................................147
Figure 20 Receive Interface Timing................................................................................148
Figure 21 Transmit Interface Timing...............................................................................149
Figure 22 CMP Timing....................................................................................................150
Figure 23 PSEL Timing...................................................................................................150
Figure 24 Sample RC Filter ............................................................................................154
Figure 25 Microprocessor Interface Read Timing...........................................................158
Figure 26 Microprocessor Interface Write Timing...........................................................159
Figure 27 TSE Input Timing............................................................................................161
Figure 28 TSE Output Timing .........................................................................................162
Figure 29 RSTB Timing...................................................................................................163
Figure 30 JTAG Port Interface Timing............................................................................165