參數(shù)資料
型號: PM5372-BI
英文描述: Telecommunication IC
中文描述: 通信集成電路
文件頁數(shù): 160/169頁
文件大小: 989K
代理商: PM5372-BI
TSE Transmission Switch Element Datasheet
Released
Proprietary and Confidential to PMC-Sierra, Inc., and for its Customers’ Internal Use
Document ID: PMC-1991258, Issue 7
160
Notes on Microprocessor Interface Write Timing:
1 A valid write cycle is defined as a logical OR of the CSB and the WRB signals.
2 In non-multiplexed address/data bus architectures, ALE should be held high so parameters
tSALW, tHALW, tVL, tSLW, and tHLW are not applicable.
3 Parameter tHAW is not applicable if address latching is used.
4 When a set-up time is specified between an input and a clock, the set-up time is the time in
nanoseconds from the 1.4 Volt point of the input to the 1.4 Volt point of the clock.
5 When a hold time is specified between an input and a clock, the hold time is the time in
nanoseconds from the 1.4 Volt point of the input to the 1.4 Volt point of the clock.
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