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| 型號(hào)： | PM5372-BI |
| 英文描述： | Telecommunication IC |
| 中文描述： | 通信集成電路 |
| 文件頁(yè)數(shù)： | 135/169頁(yè) |
| 文件大?。?/td> | 989K |
| 代理商： | PM5372-BI |
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TSE Transmission Switch Element Datasheet
Released
Proprietary and Confidential to PMC-Sierra, Inc., and for its Customers’ Internal Use
Document ID: PMC-1991258, Issue 7
135
STCTEST
The single transport chain instruction is used to test out the TAP controller and the boundary scan
register during production test. When this instruction is the current instruction, the boundary scan
register is connected between TDI and TDO. During the Capture-DR state, the device
identification code is loaded into the boundary scan register. The code can then be shifted out
output, TDO using the Shift-DR state.
12.6 Initialization Procedure
The following is a suggested initialization procedure which may be helpful when writing
initialization code for the TSE.
Set the TSE Master Configuration register to: ETSE_MODE=0, ITSE_MODE=0,
002h to 8400h
set addr
Set the CSU Control registers to: CSU_ENB=0, CSU_RSTB=1
set addresses 0020h, 0024h, 0028h, 002Ch to 0409h
Set the SSWT RJ0FP Delay register 0040H as per section 1.1
Set the SSWT TJ0FP Delay Register 0047H as per section 1.1
Set the R8FA 1 – 64 Analog Control register to: DRU_ENB=0, RX_ENB=0 and
DRU_CONTROL=1101
set addresses 0N83h, 0N8Bh, 0N93h, and 0N9Bh (N=0 to F) to CC34h
Set the ITSE 1- 16 time slot switching settings as per switching requirements.
Set the ETSE 1-16 time slot switching settings as per switching requirements.
Set the SSWT 1-16 space switching settings as per switching requirements.
Set the T8DE 1 – 64 Analog Control registers to: TXLV_ENB=0, PISO_ENB=0
set addresses 0NB5h, 0NBDh, 0NC5h, and 0NCDh (N=0 to F) to 0007h
Ensure that the CSUs show stable “l(fā)ocked” status by reading registers 0x21/0x22, 0x25/0x26,
0x29/0x2A and 0x2D/0x2E:
Read registers 0x21, 0x25, 0x29 and 0x2D – expect to see 0x01 representing the interrupt from
changes in lock state during reset.
Read registers 0x21, 0x25, 0x29 and 0x2D again – expect to see 0x00 indicating stable lock
status.
Read registers 0x22, 0x26, 0x2A and 0x2E – expect to see LOCKV bit set to 1 indicating that the
CSUs are stable in the locked state.
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