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| 型號(hào)： | PM5372-BI |
| 英文描述： | Telecommunication IC |
| 中文描述： | 通信集成電路 |
| 文件頁(yè)數(shù)： | 139/169頁(yè) |
| 文件大?。?/td> | 989K |
| 代理商： | PM5372-BI |
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TSE Transmission Switch Element Datasheet
Released
Proprietary and Confidential to PMC-Sierra, Inc., and for its Customers’ Internal Use
Document ID: PMC-1991258, Issue 7
139
In addition to device latencies, there are other sources of delay. Furthermore, these delays may
vary from link to link. For example, clock skew or differential trace lengths impose uneven
delays on individual links. The 24-word depth of the FIFOs allows these delays to be equalized
as part of the re-framing process. When the RJ0FP-RJ0DLY trigger signals the occurrence of a
frame boundary, the TSE will adjust the FIFOs read positions to realign the STS-12 streams’ J0
characters with one another. As long as the J0 characters from all the STS-12 streams are indeed
simultaneously present in their respective FIFOs when this occurs, the TSE will effectively re-
align the streams as part of the re-framing process. The large FIFO depth allows the TSE to
compensate for such differential delays as trace lengths that vary by several meters. Smaller
delay variances, such as those due to clock jitter, can be absorbed automatically by the serial
receive links. If they prove to be too large for such absorption, they will then be corrected
through the FIFO re-framing process.
In order to guarantee that the RJ0FP-RJ0DLY trigger will happen when all streams’ J0 characters
are simultaneously present within the FIFOs, it is important to choose correct values for the frame
delay register. The following example explains how frame delay register values are chosen for
the devices of a sample system. Consider the implementation shown in Figure 14. All devices
receive the global frame pulse simultaneously at time t0 (ignoring any trace length differentials).
The SPECTRA-2488 emits the J0 byte onto the TelecomBus upon receiving the global frame
pulse on the DJ0REF input. This action is entirely independent of receiving a J0 byte from the
optical line. SPECTRA-2488 pointer adjustments will define the start of the payload envelope
(the J1 byte indicates start of payload) and this payload will be outputted over the TelecomBus.
The SPECTRA-2488 can be viewed as the master by which the synchronization of the other
CHESS devices is determined. The TBS expects the four incoming eight bit 77.76 MHz
TelecomBus data paths to be synchronized and upon processing emits the serialized data with J0
character 33 clock cycles after receiving the J0 on the parallel TelecomBus. The J0 byte on each
of the twelve independent 777.6 MHz LVDS links are not exactly simultaneous and may have a
slight amount of skew relative to each other (because of presence of an 8 word FIFO on the
LVDS transmitter output). The LVDS links are then mated to the TSE through a back-plane. The
TSE is programmed (via indirect register access of the RJ0DLY[13:0] word) to expect the J0 byte
a certain number of clock cycles after it receives the global frame pulse.
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