參數(shù)資料
型號: PM5372-BI
英文描述: Telecommunication IC
中文描述: 通信集成電路
文件頁數(shù): 105/169頁
文件大?。?/td> 989K
代理商: PM5372-BI
TSE Transmission Switch Element Datasheet
Released
Proprietary and Confidential to PMC-Sierra, Inc., and for its Customers’ Internal Use
Document ID: PMC-1991258, Issue 7
105
Register 0NA2H: Port Set #1 - #16 ITSE Configuration
Bit
Type
Function
Default
Bit 15
Unused
X
Bit 14
Unused
X
Bit 13
Unused
X
Bit 12
Unused
X
Bit 11
Unused
X
Bit 10
Unused
X
Bit 9
Unused
X
Bit 8
Unused
X
Bit 7
Unused
X
Bit 6
Unused
X
Bit 5
Unused
X
Bit 4
Unused
X
Bit 3
R
IACTIVE
X
Bit 2
R/W
IPSEL
0
Bit 1
R/W
IJ0RORDR
0
Bit 0
R/W
ICOAPE
0
These registers provide page selection, active page indication, J0 reordering mode, and
interrupt masking control for ITSE blocks #1 through #16.
ICOAPE
The change of active page interrupt enable bit (ICOAPE) masks the contribution of the
change of active page event indication bit (ICOAPI) in the ISTI block to INTB. When
ICOAPE is high, INTB is asserted low when ICOAPI is high. INTB is not affected by the
value of ICOAPI when ICOAPE is low.
IJ0RORDR
The incoming J0 reorder bit controls the reordering of J0/Z0 bytes in the four STS-12
datastreams through the
n
th ITSE block. Time slot interchange of the J0/Z0 bytes in the
n
th
ITSE is suspended when J0/Z0 reordering is disabled. When IJ0RORDR is set low, the J0/Z0
bytes are not reordered. When IJ0RORDR is set high, J0/Z0 byte reordering is enabled. If J0
reordering is enabled, J0 masking should also be enabled in the upstream R8Fas to prevent
K28.5 characters from being switched to a position other than J0. J0 masking is done using
the J0MASK bit in register 0N80H, 0N88H, 0N90H, and 0N98H.
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