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| 型號(hào)： | PM5372-BI |
| 英文描述： | Telecommunication IC |
| 中文描述： | 通信集成電路 |
| 文件頁數(shù)： | 36/169頁 |
| 文件大小： | 989K |
| 代理商： | PM5372-BI |
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TSE Transmission Switch Element Datasheet
Released
Proprietary and Confidential to PMC-Sierra, Inc., and for its Customers’ Internal Use
Document ID: PMC-1991258, Issue 7
36
Table 2 Pin Description TSE Control and Clocking (5 Signals)
Pin Name
Type
Pin No.
Function
SYSCLK
Input
B5
System Clock.
The system clock signal (SYSCLK) is the master clock for
the TSE device. SYSCLK must be a 77.76 MHz clock, with a nominal 50%
duty cycle.
RJ0FP
Input
C5
Receive Serial Interface Frame Pulse.
The receive serial interface frame
pulse signal (RJ0FP) provides system timing for the receive serial
interface. RJ0FP is supplied in common to all devices in a system
containing one or more TSE devices. RJ0FP is set high once every 9720
SYSCLK cycles, or multiple thereof. A software configurable delay from
RJ0FP is used to indicate that the J0 frame boundary 8B/10B characters
have been delivered on all the receive serial data links (RP[64:1]/RN[64:1])
and are ready for processing by the time-space-time switching elements.
RJ0FP is sampled on the rising edge of SYSCLK.
TJ0FP
Output
G2
Transmit Serial Interface Frame Pulse.
The transmit serial interface
frame pulse signal (TJ0FP) should be treated as an asynchronous output
which can be used to give a rough estimate of when the J0 character is
transmitted on the serial TelecomBus. TJ0FP is set high once every 9720
SYSCLK cycles. The pulse timing relative to the STS-12 frame is
determined by the TJ0DLY register. It is recommended that the register is
set so the TJ0FP pulse indicates that the J0 frame boundary 8B/10B
character has been serialised out on all the transmit serial data links
(TP[64:1]/TN[64:1]). TJ0FP is for diagnostic purposes only and is not
intended as a reference for timing.
CMP
Input
E4
Connection Memory Page.
The transmit connection memory page select
signal (CMP) controls the selection of the connection memory page in TSE.
In each block with connection memory, CMP is XORed with a software
configurable page select bit. When the result is high, connection memory
page 1 is selected. When the result is low, connection memory page 0 is
selected. CMP is sampled on the rising edge of SYSCLK at the RJ0FP
frame position. Refer to CMP functional timing for an indication of when a
change to CMP takes effect.
RSTB
Input
AU35
Reset Enable Bar.
The active low reset signal (RSTB) provides an
asynchronous reset for the TSE. RSTB is a Schmitt triggered input with an
integral pull-up resistor.
Table 3 Pin Description Microprocessor Interface (34 Signals)
Pin Name
Type
Pin No.
Function
CSB
Input
E3
Chip Select Bar.
The active low chip select signal (CSB) controls
microprocessor access to registers in the TSE device. CSB is set low
during TSE Microprocessor Interface Port register accesses. CSB is set
high to disable microprocessor accesses.
If CSB is not required (i.e. register accesses controlled using RDB and
WRB signals only), CSB should be connected to an inverted version of the
RSTB input.
RDB
Input
F2
Read Enable Bar.
The active low read enable bar signal (RDB) controls
microprocessor read accesses to registers in the TSE device. RDB is set
low and CSB is also set low during TSE Microprocessor Interface Port
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