- 您現(xiàn)在的位置：買(mǎi)賣IC網(wǎng) > PDF目錄368064 > PM5372-BI Telecommunication IC PDF資料下載
參數(shù)資料
| 型號(hào)： | PM5372-BI |
| 英文描述： | Telecommunication IC |
| 中文描述： | 通信集成電路 |
| 文件頁(yè)數(shù)： | 53/169頁(yè) |
| 文件大小： | 989K |
| 代理商： | PM5372-BI |
第1頁(yè)第2頁(yè)第3頁(yè)第4頁(yè)第5頁(yè)第6頁(yè)第7頁(yè)第8頁(yè)第9頁(yè)第10頁(yè)第11頁(yè)第12頁(yè)第13頁(yè)第14頁(yè)第15頁(yè)第16頁(yè)第17頁(yè)第18頁(yè)第19頁(yè)第20頁(yè)第21頁(yè)第22頁(yè)第23頁(yè)第24頁(yè)第25頁(yè)第26頁(yè)第27頁(yè)第28頁(yè)第29頁(yè)第30頁(yè)第31頁(yè)第32頁(yè)第33頁(yè)第34頁(yè)第35頁(yè)第36頁(yè)第37頁(yè)第38頁(yè)第39頁(yè)第40頁(yè)第41頁(yè)第42頁(yè)第43頁(yè)第44頁(yè)第45頁(yè)第46頁(yè)第47頁(yè)第48頁(yè)第49頁(yè)第50頁(yè)第51頁(yè)第52頁(yè)當(dāng)前第53頁(yè)第54頁(yè)第55頁(yè)第56頁(yè)第57頁(yè)第58頁(yè)第59頁(yè)第60頁(yè)第61頁(yè)第62頁(yè)第63頁(yè)第64頁(yè)第65頁(yè)第66頁(yè)第67頁(yè)第68頁(yè)第69頁(yè)第70頁(yè)第71頁(yè)第72頁(yè)第73頁(yè)第74頁(yè)第75頁(yè)第76頁(yè)第77頁(yè)第78頁(yè)第79頁(yè)第80頁(yè)第81頁(yè)第82頁(yè)第83頁(yè)第84頁(yè)第85頁(yè)第86頁(yè)第87頁(yè)第88頁(yè)第89頁(yè)第90頁(yè)第91頁(yè)第92頁(yè)第93頁(yè)第94頁(yè)第95頁(yè)第96頁(yè)第97頁(yè)第98頁(yè)第99頁(yè)第100頁(yè)第101頁(yè)第102頁(yè)第103頁(yè)第104頁(yè)第105頁(yè)第106頁(yè)第107頁(yè)第108頁(yè)第109頁(yè)第110頁(yè)第111頁(yè)第112頁(yè)第113頁(yè)第114頁(yè)第115頁(yè)第116頁(yè)第117頁(yè)第118頁(yè)第119頁(yè)第120頁(yè)第121頁(yè)第122頁(yè)第123頁(yè)第124頁(yè)第125頁(yè)第126頁(yè)第127頁(yè)第128頁(yè)第129頁(yè)第130頁(yè)第131頁(yè)第132頁(yè)第133頁(yè)第134頁(yè)第135頁(yè)第136頁(yè)第137頁(yè)第138頁(yè)第139頁(yè)第140頁(yè)第141頁(yè)第142頁(yè)第143頁(yè)第144頁(yè)第145頁(yè)第146頁(yè)第147頁(yè)第148頁(yè)第149頁(yè)第150頁(yè)第151頁(yè)第152頁(yè)第153頁(yè)第154頁(yè)第155頁(yè)第156頁(yè)第157頁(yè)第158頁(yè)第159頁(yè)第160頁(yè)第161頁(yè)第162頁(yè)第163頁(yè)第164頁(yè)第165頁(yè)第166頁(yè)第167頁(yè)第168頁(yè)第169頁(yè)
TSE Transmission Switch Element Datasheet
Released
Proprietary and Confidential to PMC-Sierra, Inc., and for its Customers’ Internal Use
Document ID: PMC-1991258, Issue 7
53
The T8DE will not correct running disparity violations for these specific codes: K28.0-, K28.0+,
K28.4-, K28.4+, K27.7-, K27.7+, K 28.7-, K28.7+, K29.7-, K29.7+, K30.7-, K30.7+, K23.7-,
K23.7+.
The timing of egress LVDS signals requires that this block include a FIFO to cross from the
internal TSE time domain to the time domain of the egress LVDS units. The clocks driving these
two domains originate in the same master clock, but may have varying skew.
Microprocessor access to the T8DE allows the control and monitoring of its activities. FIFO
status can be monitored and corrected. The T8DE can be configured to insert J0s into the
datastream. The T8DE also provides reset, enable and test control over its associated PISO and
TXLV analog blocks.
9.7
Clock Synthesis and Transmit Reference Digital Wrapper (CSTR)
The CSTR is an digital wrapper for the CSU and TXREF LVDS analog locks. It provides
microprocessor access for resetting and disabling the CSU. It also monitors the lock state of the
CSU on the system clock.
9.8
Fabric Latency
The flow of STS-1 samples from ingress LVDS to egress LVDS has variable latency, depending
on the timing of the arriving LVDS stream, and the clock variation on the egress LVDS drivers. A
reasonable estimate of the TSE’s latency can be arrived at by making assumptions about the
depths of the receive and transmit FIFOs: we assume the “J0” timing is set to maintain about 12
samples in the ingress FIFO; the egress FIFO is designed to be centered at 4 samples – so
typically delay due to FIFOs will be 16 clock cycles. Maximum delay through the FIFOs can be
32 cycles. The R8FA imposes an additional 6 cycles of latency in addition to the ingress FIFO
delay. The T8DE imposes 4 cycles of latency in addition to the egress FIFO delay. The latency
through the time and space switch stages is 32 cycles. Data latency through the analog blocks is
around 90 ns or 7 clock cycles with 5 cycles delay through the RX analog blocks and 2 cycles
delay through the transmit analog blocks. By summing all the delays the typical latency of the
TSE is 65 clock cycles or 836 ns. With worst case conditions in both FIFOs, latency rises to 81
clock cycles or 1044 ns.
9.9
JTAG Support
The TSE provides JTAG support for testing device interconnection on a PC board.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| PM5380 | PMC-2010299 S/UNI-8x155 Telecom Standard Product Data Sheet [1.91 MB] |
| PM554 | Programmable Quad Supply Monitor with Adjustable Reset and Watchdog Timers; Package: SSOP; No of Pins: 16; Temperature Range: -40°C to +85°C |
| PM555 | 1 to 10 watt encapsulated power modules |
| PM556 | Precision Quad Supply Monitor in 6-Lead SOT-23; Package: SOT; No of Pins: 6; Temperature Range: 0°C to +70°C |
| PM560 | Precision Quad Supply Monitor in 6-Lead SOT-23; Package: SOT; No of Pins: 6; Temperature Range: 0°C to +70°C |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| PM5372BIP | 制造商:PMC-Sierra 功能描述: |
| PM5372-BI-P | 制造商:PMC-Sierra 功能描述: |
| PM5376HFI | 制造商:PMC-Sierra 功能描述: |
| PM5377 | 制造商:PMC 制造商全稱:PMC 功能描述:Single Chip 96-Port STS-1/STM-0 Cross-Connect |
| PM537CE | 制造商:ARTESYN 制造商全稱:Artesyn Technologies 功能描述:Single, dual and triple output 1 to 10.5 Watt AC/DC encapsulated modules |
發(fā)布緊急采購(gòu)，3分鐘左右您將得到回復(fù)。