參數(shù)資料
型號： PM5372-BI
英文描述： Telecommunication IC
中文描述： 通信集成電路
文件頁數(shù)： 53/169頁
文件大?。?/td> 989K
代理商： PM5372-BI
TSE Transmission Switch Element Datasheet
Released
Proprietary and Confidential to PMC-Sierra, Inc., and for its Customers’ Internal Use
Document ID: PMC-1991258, Issue 7
53
The T8DE will not correct running disparity violations for these specific codes: K28.0-, K28.0+,
K28.4-, K28.4+, K27.7-, K27.7+, K 28.7-, K28.7+, K29.7-, K29.7+, K30.7-, K30.7+, K23.7-,
K23.7+.
The timing of egress LVDS signals requires that this block include a FIFO to cross from the
internal TSE time domain to the time domain of the egress LVDS units. The clocks driving these
two domains originate in the same master clock, but may have varying skew.
Microprocessor access to the T8DE allows the control and monitoring of its activities. FIFO
status can be monitored and corrected. The T8DE can be configured to insert J0s into the
datastream. The T8DE also provides reset, enable and test control over its associated PISO and
TXLV analog blocks.
9.7
Clock Synthesis and Transmit Reference Digital Wrapper (CSTR)
The CSTR is an digital wrapper for the CSU and TXREF LVDS analog locks. It provides
microprocessor access for resetting and disabling the CSU. It also monitors the lock state of the
CSU on the system clock.
9.8
Fabric Latency
The flow of STS-1 samples from ingress LVDS to egress LVDS has variable latency, depending
on the timing of the arriving LVDS stream, and the clock variation on the egress LVDS drivers. A
reasonable estimate of the TSE’s latency can be arrived at by making assumptions about the
depths of the receive and transmit FIFOs: we assume the “J0” timing is set to maintain about 12
samples in the ingress FIFO; the egress FIFO is designed to be centered at 4 samples – so
typically delay due to FIFOs will be 16 clock cycles. Maximum delay through the FIFOs can be
32 cycles. The R8FA imposes an additional 6 cycles of latency in addition to the ingress FIFO
delay. The T8DE imposes 4 cycles of latency in addition to the egress FIFO delay. The latency
through the time and space switch stages is 32 cycles. Data latency through the analog blocks is
around 90 ns or 7 clock cycles with 5 cycles delay through the RX analog blocks and 2 cycles
delay through the transmit analog blocks. By summing all the delays the typical latency of the
TSE is 65 clock cycles or 836 ns. With worst case conditions in both FIFOs, latency rises to 81
clock cycles or 1044 ns.
9.9
JTAG Support
The TSE provides JTAG support for testing device interconnection on a PC board.
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