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| 型號(hào)： | PM5372-BI |
| 英文描述： | Telecommunication IC |
| 中文描述： | 通信集成電路 |
| 文件頁(yè)數(shù)： | 128/169頁(yè) |
| 文件大?。?/td> | 989K |
| 代理商： | PM5372-BI |
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TSE Transmission Switch Element Datasheet
Released
Proprietary and Confidential to PMC-Sierra, Inc., and for its Customers’ Internal Use
Document ID: PMC-1991258, Issue 7
128
12.3 LVDS Hot Swapping
The LVDS electrical interface differs from a standard CMOS interface; there is no inherent
problem in leaving the LVDS inputs floating. Note that the LVDS receiver consists of a
differential amplifier with a wide common-mode range. The power dissipation is independent of
the data transitions (that is, if the input is connected). There is an internal 100 termination
across the positive and negative input. Floating inputs will settle to an arbitrary voltage (between
VDD and VSS) determined by leakage paths. Regardless of this arbitrary voltage, the input
structure of the receiver will operate in its proper range and the receiver output will be logic 1 or
0 depending on internal offsets. Noise events (power supply noise, crosstalk) may induce the
receiver to toggle randomly, generating "ambiguous" data.
Unused links should be disabled in software. This will ensure that the power consumption for
those links will be reduced to nearly 0 mW. There is no requirement for how quickly the link
should be disabled. Disabling the link simply results in lower power dissipation since the
circuitry will be shut down. This action is not mandatory, but is good practice.
During a hot-swapping situation, there will be no electrical damage on the LVDS inputs provided
that maximum ratings are not exceeded (see absolute maximum ratings section 14)
.
The “hot-
swap” channel can be left enabled and the device will sync up once the far end transmitter is
connected. There are no effects on other channels. Hot swapping of cards is still allowed by
reprogramming of the links in software.
12.4 LVDS Trace Lengths
The TSE utilizes 64 different input and output differential LVDS pairs. It is critical to match the
lengths of the positive and negative traces of each differential pair to minimize skew and
maximize the eye opening. However, matching one differential pair to another pair is not as
important. The high-speed serial LVDS links are connected to a 24 word (10 bit byte) FIFO. Of
this 24 word FIFO, 8 words should be allocated for clock skew and wander between cards or
within devices. The remaining 16 words are then available to accommodate clock skew and
wander between cards or within devices, along with differences in trace lengths between LVDS
pairs.
The 16 word FIFO yields an allowable inter-link delay differential of 205.8 ns or 41.2m. This is
calculated as follows:
16 words x 10 bits/word = 160 bits of margin in FIFO
1/(777.6 Mb/s) = 1.29 ns/bit on the serial link
160 bits x 1.29 ns/bit = 205.8 ns of margin = 16 clock cycles (at 77.76 MHz)
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