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參數(shù)資料
| 型號： | PM5372-BI |
| 英文描述： | Telecommunication IC |
| 中文描述： | 通信集成電路 |
| 文件頁數(shù)： | 102/169頁 |
| 文件大?。?/td> | 989K |
| 代理商： | PM5372-BI |
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TSE Transmission Switch Element Datasheet
Released
Proprietary and Confidential to PMC-Sierra, Inc., and for its Customers’ Internal Use
Document ID: PMC-1991258, Issue 7
102
TSOUT[3:0]
The indirect STS-1/STM-0 output time slot (TSOUT[3:0]) select bits for the ITSE block
indicate the STS-1/STM-0 output time slot within the datastream selected by DOUTSEL[1:0]
that is accessed in the current indirect access. Valid time-slot values are ‘b0001 to ‘b1100.
TSOUT[3:0]
STS-1/STM-0 time slot #
0000
Invalid time slot
0001-1100
Time slot #1 to time slot #12
1101-1111
Invalid time slot
PAGE
The connection memory page select bit (PAGE) selects the connection memory page to be
accessed in the current indirect access. When PAGE is set high, page 1 is selected. When
Page is set low, PAGE 0 is selected.
RWB
The indirect access control bit (RWB) selects between a configure (write) or interrogate
(read) access to the control pages for the ITSE block. Writing a logic 0 to RWB triggers an
indirect write operation. Data to be written is taken for the ITSE Indirect Data register.
Writing a logic 1 to RWB triggers an indirect read operation. The data read from the control
pages is stored in the ITSE Indirect Data register after the BUSY bit has cleared.
BUSY
The indirect access status bit (BUSY) reports the progress of an indirect access for the ITSE
block. BUSY is set to logic 1 when this register is written, triggering an access. It remains
logic 1 until the access is complete at which time it is set to logic 0. These registers should be
polled to determine when new data is available in the ITSE Indirect Data Register or when
another write access can be initiated. The BUSY bit shows a default of “x”. This does not
require the bit to be cleared after a reset since the bit resets to 0 a few clock cycles after a
reset. The bit is undefined for a short period (a few clock cycles) after a reset but the user
will never read “1” as the bit would clear before the bit is queried.
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| PM5372BIP | 制造商:PMC-Sierra 功能描述: |
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| PM537CE | 制造商:ARTESYN 制造商全稱:Artesyn Technologies 功能描述:Single, dual and triple output 1 to 10.5 Watt AC/DC encapsulated modules |
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