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| 型號(hào)： | PM5372-BI |
| 英文描述： | Telecommunication IC |
| 中文描述： | 通信集成電路 |
| 文件頁(yè)數(shù)： | 47/169頁(yè) |
| 文件大?。?/td> | 989K |
| 代理商： | PM5372-BI |
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TSE Transmission Switch Element Datasheet
Released
Proprietary and Confidential to PMC-Sierra, Inc., and for its Customers’ Internal Use
Document ID: PMC-1991258, Issue 7
47
The TXLV uses a reference current and voltage from the TXLVREF block to control the output
differential voltage amplitude and the output common-mode voltage.
Unused links should be disabled in software. In this case the power for that link will be nearly
0mW. There is no requirement for how quickly this should be done. It simply results in lower
power dissipation since circuitry will be shut down. This is not mandatory for the device to
operate properly but is a good practice since it improves margins.
Hot-swapping is supported. The channel can be left enabled at all time and the device will sync
up once the far end receiver is connected. There will be no effect on other channels.
There are 64 instances of the TXLV block on the TSE.
9.1.3
LVDS Transmit Reference (TXREF)
The TXLVREF provides an on-chip bandgap voltage reference (1.20V ±5%) and a precision
current to the TXLV (777.6 Mb/s LVDS Transmitter) block’s. The reference voltage is used to
control the common-mode level of the TXLV output, while the reference current is used to
control the output amplitude.
The precision currents are generated by forcing the reference voltage across an external, off-chip
3.16k (±1%) resistor. The resulting current is then mirrored through several individual
reference current outputs, so each TXLV receives its own reference current.
There are four instances of the TXREF on the TSE.
9.1.4
Data Recovery Unit (DRU)
The DRU is a fully integrated data recovery and serial to parallel converter that can be used for
777.6 Mb/s NRZ data. 8B/10B block code is used to guarantee transition density for optimal
performance.
The DRU recovers data and outputs a 10-bit word synchronized with a line rate divided-by-10
gated clock to allow frequency deviations between the data source and the local oscillator. The
output clock is not a recovered clock. The DRU accumulates 10 data bits and outputs them on
the next clock edge. If 10 bits are not available for transfer at a given clock cycle, the output
clock is gated.
The DRU provides moderate high frequency jitter tolerance suitable for inter-chip serial link
applications. It can support frequency deviations up to 100ppm.
There are 64 instances of the DRU on the TSE.
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