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| 型號(hào)： | PM5372-BI |
| 英文描述： | Telecommunication IC |
| 中文描述： | 通信集成電路 |
| 文件頁(yè)數(shù)： | 38/169頁(yè) |
| 文件大?。?/td> | 989K |
| 代理商： | PM5372-BI |
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TSE Transmission Switch Element Datasheet
Released
Proprietary and Confidential to PMC-Sierra, Inc., and for its Customers’ Internal Use
Document ID: PMC-1991258, Issue 7
38
Table 4 Pin Description JTAG Port (5 Signals)
Pin Name
Type
Pin No.
Function
TCK
Input
AR2
Test Clock.
The JTAG test clock signal (TCK) provides timing for test
operations that are carried out using the IEEE P1149.1 test access port.
TMS
Input
AR3
Test Mode Select.
The JTAG test mode select signal (TMS) controls the
test operations that are carried out using the IEEE P1149.1 test access
port. TMS is sampled on the rising edge of TCK. TMS has an integral pull-
up resistor.
TDI
Input
AR1
Test Data Input.
The JTAG test data input signal (TDI) carries test data
into the TSE via the IEEE P1149.1 test access port. TDI is sampled on the
rising edge of TCK. A 30 Kohm external pull-up resistor is recommended
on this pin.
TDO
Tri-state E2
Test Data Output.
The JTAG test data output signal (TDO) carries test
data out of the TSE via the IEEE P1149.1 test access port. TDO is
updated on the falling edge of TCK. TDO is a tri-state output which is
inactive except when scanning of data is in progress.
TRSTB
Input
AV35
Test Reset Bar.
The active low JTAG test reset signal (TRSTB) provides
an asynchronous TSE test access port (TAP) controller reset via the IEEE
P1149.1 test access port. TRSTB is a Schmitt triggered input with an
integral pull-up resistor.
The TAP controller must be placed in the Test-Logic-Reset state after
applying power to the device to guarantee correct device operation. This is
easily accomplished by connecting TRSTB to the RSTB input and
performing a device reset, but is not necessary if another method of
resetting the TAP controller is implemented.
Table 5 Pin Description External Resistors (8 Signals)
Pin Name
Type
Pin No.
Function
RES[4]
RES[3]
RES[2]
RES[1]
Analog
Input
B7
G38
AV33
AN2
Reference Resistor Connection.
An off-chip 3.16k ±1% resistor is
connected between each positive resistor reference pin RES[I] and the
corresponding Kelvin ground contact RESK[I].
RESK[4]
RESK[3]
RESK[2]
RESK[1]
Analog
Input
A7
G39
AW33
AN1
Reference Resistor Connection.
An off-chip 3.16k ±1% resistor is
connected between each positive resistor reference pin RES[I] and the
corresponding Kelvin ground contact RESK[I].
Table 6 Pin Description Analog Test Bus (8 Signals)
Pin Name
Type
Pin No.
Function
ATB0[4]
ATB0[3]
ATB0[2]
ATB0[1]
Analog
D32
AM36
AT8
H4
These pins are used for PMC testing only and should be directly connected
to ground.
ATB1[4]
Analog
D31
These pins are used for PMC testing only and should be directly connected
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