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| 型號(hào)： | PM5372-BI |
| 英文描述： | Telecommunication IC |
| 中文描述： | 通信集成電路 |
| 文件頁(yè)數(shù)： | 150/169頁(yè) |
| 文件大?。?/td> | 989K |
| 代理商： | PM5372-BI |
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TSE Transmission Switch Element Datasheet
Released
Proprietary and Confidential to PMC-Sierra, Inc., and for its Customers’ Internal Use
Document ID: PMC-1991258, Issue 7
150
Figure 22 CMP Timing
TP[
X
]/
TN[
X
]
...
SYSCLK
RJ0FP
S4,3/
A2
S1,1/J0
S2,1/
Z0
...
Valid
CMP
X
X
RJ0DLY + Delay (40 to 47
cycles) to J0
S1,1/
A1
S2,1/
A1
...
...
...
...
S3,1/
A1
Delay to second frame A1:
19416 cycles
Figure 23 below shows the delay from the PSEL bits, SPSEL, IPSEL, and EPSEL, to their effect
datastream at the transmit serial data links. The PSEL bits are written asynchronously with
respect to the system clock, so use of the PSEL bits to effect switching connection memory pages
should be avoided if switching on a particular frame is required. Additionally the user can avoid
changing PSEL bits close to the point in time when PSEL bits are sampled by the synchronous
logic. If the frame pulse occurs at time 0, IPSEL is sampled at time RJ0DLY, SPSEL is sampled
at time RJ0DLY+15, and EPSEL is sampled at time RJ0DLY+17. Switchover is delayed
internally for approximately a frame. Page switchover occurs on frame boundaries, with the A1
bytes switching on the new settings. The frame switched by the newly selected connection
memory page first appears on the transmit serial data links between offset RJ0DLY+40+9699
cycles and RJ0DLY+47+9696 cycles.
Figure 23 PSEL Timing
TP[
X
]/
TN[
X
]
...
SYSCLK
RJ0FP
S4,3/
A2
S1,1/J0
S2,1/
Z0
...
PSEL
RJ0DLY+ Delay(40-47 cycles)
to J0
S1,1/
A1
S2,1/
A1
...
...
...
...
S3,1/
A1
Delay to next frame A1: 9696
cycles
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|---|---|
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