參數資料
型號: PM5372-BI
英文描述: Telecommunication IC
中文描述: 通信集成電路
文件頁數: 116/169頁
文件大?。?/td> 989K
代理商: PM5372-BI
TSE Transmission Switch Element Datasheet
Released
Proprietary and Confidential to PMC-Sierra, Inc., and for its Customers’ Internal Use
Document ID: PMC-1991258, Issue 7
116
CENTER:
The FIFO centering control bit (CENTER) controls the separation of the T8DE FIFO read
and write pointers. CENTER is a write only bit. When a logic high is written to CENTER,
and the current FIFO depth is not in the range of 3, 4 or 5 characters, the FIFO depth is forced
to be 3 or 4 8B/10B characters deep, with a momentary data corruption. Writing to the
CENTER bit when the FIFO depth is in the 3, 4 or 5 character range produces no effect.
CENTER always returns a logic low when read.
Reserved
The Reserved bit must be set to the indicated default value for correct operation of the TSE.
TPINS
The Test Pattern Insertion (TPINS) controls the insertion of test pattern in the outgoing data
stream for jitter testing purpose. When this bit is set high, TP[9:0] in the T8DE Test Pattern
register is selected for output. TPINS takes precedence over J0INS, inserted K28.5 will be
overwritten with the test pattern.
FIFOERRE
The FIFO underrun/overrun error interrupt enable bit (FIFOERRE) masks the contribution of
the FIFO underrun/overrun event indication bit (FIFOERRI) in the T8DE block to INTB.
When FIFOERRE is high, INTB is asserted low when FIFOERRI is high. INTB is not
affected by the value of FIFOERRI when FIFOERRE is low.
J0INS
The J0 byte Insertion (J0INS) controls the insertion of first J0 bytes in the outgoing data
stream. When this bit is set to logic 1, a K28.5 character is inserted at the J0 byte position on
every frame, overwriting the data in that position (TSE inserted AIS included). When J0INS
is set to logic 0, the outgoing data stream is not modified.
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