參數(shù)資料
型號(hào): PM5372-BI
英文描述: Telecommunication IC
中文描述: 通信集成電路
文件頁數(shù): 84/169頁
文件大小: 989K
代理商: PM5372-BI
TSE Transmission Switch Element Datasheet
Released
Proprietary and Confidential to PMC-Sierra, Inc., and for its Customers’ Internal Use
Document ID: PMC-1991258, Issue 7
84
Register 0040H: SSWT RJ0FP Delay
Bit
Type
Function
Default
Bit 15
Unused
X
Bit 14
Unused
X
Bit 13
R/W
RJ0DLY[13]
0
Bit 12
R/W
RJ0DLY[12]
0
Bit 11
R/W
RJ0DLY[11]
0
Bit 10
R/W
RJ0DLY[10]
0
Bit 9
R/W
RJ0DLY[9]
0
Bit 8
R/W
RJ0DLY[8]
0
Bit 7
R/W
RJ0DLY[7]
0
Bit 6
R/W
RJ0DLY[6]
0
Bit 5
R/W
RJ0DLY[5]
0
Bit 4
R/W
RJ0DLY[4]
0
Bit 3
R/W
RJ0DLY[3]
0
Bit 2
R/W
RJ0DLY[2]
0
Bit 1
R/W
RJ0DLY[1]
0
Bit 0
R/W
RJ0DLY[0]
0
This register controls the delay from the RJ0FP input signal to the time when the TSE may safely
process the J0 characters delivered by the receive data links (RP [64:1]/RN[64:1]).
RJ0DLY[13:0]
The receive transport frame delay bits (RJ0DLY[13:0]) controls the delay from the RJ0FP
pulse clock cycle, in SYSCLK cycles, inserted by the TSE before processing the J0
characters delivered by the receive serial data links. RJ0DLY is set such that after the
specified delay, all active receive links would have delivered the J0 character to the receive
FIFO in the R8FA. RJ0DLY has valid range between 1 to 9719 inclusive. The relationships
of RJ0FP, RJ0DLY[13:0] and the system configuration are described in Figure 20, Figure 21,
and Figure 22.
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