參數(shù)資料
型號(hào): T8100A
英文描述: H.100/H.110 Interface and Time-Slot Interchangers
中文描述: H.100/H.110接口和時(shí)隙Interchangers
文件頁(yè)數(shù): 105/112頁(yè)
文件大小: 1408K
代理商: T8100A
Lucent Technologies Inc.
101
Advance Data Sheet
November 1999
H.100/H.110 Interfaces and Time-Slot Interchangers
Ambassador T8100A, T8102, and T8105
Appendix A. Application of Clock Modes
(continued)
5-6132bF
Figure 38. T1, Slave to CT Bus, Clock Source Is Either a 16 MHz or a 4 MHz or a 2 MHz and Frame, NETREF
Source = 1.544 MHz from Trunk
FRAME
SEL.
x16
4 MHz
2 MHz
FRAME SYNC
DPLL
NETREF
DIVIDE-BY-N
DIVIDE REGISTER
RCLOCK
SELECT
DIVIDE-
BY-4
GP6
GP7
NETREF
INT/EXT
SELECT
BIT SLIDER
CONTROLS
BIT SLIDER
STATE
MACHINES
PLL #2
PLL #2 BYPASS
RATE SELECT
PRIREFOUT
4MHzIN
3MHzIN
TCLKOUT
TCLKOUT
ENABLE
SELECT
x8
NET-
REF
SEL.
÷
BY 8
NETREF
SELECT
/CT_FRAME_A
/CT_FRAME_B
/FR_COMP
SEL.
CLOCK
SEL.
AND
INPUT
STATE
MACH.
1.544 MHz
L_REF7
CT_C8
CLKB
/C16
±
/C4
C2
SCLK
SCLKX2
XTALIN
TODJAT/GP6
FROMDJAT/GP7
L_SC CTL
FRAME
FRAME
SEC8K
FRAME
FRAME
EN_B
C8
C8
EN_A
CT_NETREF1
CT_C8_A
/CT_FRAME_A
CT_C8_B
/CT_FRAME_B
COMPATIBILITY
CLOCKS DIRECTION
/CT16
±
C2
/C4
SCLK
SCLKX2
/FR_COMP
L_SC0
SCSEL
4.096 MHz
(1 OF 4
L_SC[1:3]
NOT SHOWN)
16.384 MHz
2.048 MHz
4.096 MHz
2.048 MHz
8.192 MHz
8.192 MHz
2.048 MHz
4.096 MHz
8.192 MHz
16.384 MHz
PLL#2
÷
2
(FALLBACK PATH)
4.096 MHz
RESOURCE
DIVIDE-BY-N
DIVIDE REGISTER
MAIN
DIVIDE-BY-N
DIVIDE REGISTER
DIVIDE-
BY-2
CT_NETREF
FRAMERS
L_REF0
1.5 MHz DJAT
DJAT BYPASS
(AND GP6/7 ENABLE)
JITTER ATTENUATED
MULTICLOCK ADAPTER
EN_NETREF1
CT_NETREF2
EN_NETREF2
x16
x32
PLL #1
PLL #1
BYPASS
RATE SELECT
65.536 MHz
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