參數(shù)資料
型號(hào)： T8100A
英文描述： H.100/H.110 Interface and Time-Slot Interchangers
中文描述： H.100/H.110接口和時(shí)隙Interchangers
文件頁數(shù)： 68/112頁
文件大?。?/td> 1408K
代理商： T8100A
64
Lucent Technologies Inc.
Advance Data Sheet
November 1999
H.100/H.110 Interfaces and Time-Slot Interchangers
Ambassador T8100A, T8102, and T8105
2 Architecture and Functional Description
(continued)
2.8 The JTAG Test Access Port
2.8.1 Overview of the JTAG Architecture
Tap
A 5-pin test access port, consisting of input pins TCK, TMS, TDI, TDO,
and TRST, provides the standard interface to the test logic. TRST is an
active-low signal that resets the circuit.
TAP Controller
The TAP controller implements the finite state machine which controls the
operation of the test logic as defined by the standard. The TMS input
value sampled on the rising edge of TCK controls the state transitions.
The state diagram underlying the TAP controller is shown below.
Instruction Register (JIR)
A 3-bit scannable JTAG instruction register that communicates data or
commands between the TAP and the devices during test or HDS opera-
tions.
Boundary-Scan Register (JBSR)
A 211-bit JTAG boundary-scan register containing one scannable register
cell for every I/O pin and every 3-state enable signal of the device, as
defined by the standard. JBSR can capture from parallel inputs or update
into parallel outputs for every cell in the scan path. JBSR may be config-
ured into three standard modes of operation (EXTEST, INTEST, and
SAMPLE) by scanning the proper instruction code into the instruction reg-
ister (JIR). An in-depth treatment of the boundary-scan register, its physi-
cal structure, and its different cell types is given in Table 62.
Bypass Register (JBPR)
A 1-bit long JTAG bypass register to bypass the boundary-scan path of
nontargeted devices in board environments as defined by the standard.
2.8.2 Overview of the JTAG Instructions
The JTAG block supports the public instructions as shown in the table below.
Table 61. JTAG Instruction Set
Instruction Mnemonics
EXTEST
SAMPLE
Reserved
Reserved
Reserved
Reserved
Reserved
BYPASS
Instruction Codes
000
001
010
011
100
101
110
111
Public/Private
Public
Public
—
—
—
—
—
Public
Description
Select B-S register in extest mode
Select B-S register in sample mode
—
—
—
—
—
Select BYPASS register
相關(guān)PDF資料
PDF描述
T8102A H.100/H.110 Interface and Time-Slot Interchangers
T8105A H.100/H.110 Interface and Time-Slot Interchangers
T8100 H.100/H.110 Interface and Time-Slot Interchanger
T8110 Version History
T8301 T8301 Internet Protocol Telephone Phone-On-A-Chip⑩ IP Solution DSP
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
T8100A-BAL 制造商:Alcatel-Lucent 功能描述:ELECTRONIC COMPONENT
T8100A-BAL4DB 制造商:AGERE 功能描述:
T8100-D 制造商:GE Sensing & Inspection Technologies 功能描述:CO2/TEMP SENS WALL MNT DUAL OUT
T8100-E 制造商:GE Sensing & Inspection Technologies 功能描述:TRANSMITTER, CO2, HUMIDITY, TEMP 制造商:GE MEASUREMENT & CONTROL 功能描述:TRANSMITTER, CO2, HUMIDITY, TEMP; Plug Type:- ;RoHS Compliant: Yes 制造商:GE MEASUREMENT & CONTROL/GE SENSING 功能描述:TRANSMITTER, CO2, HUMIDITY, TEMP; Plug Type:- ;RoHS Compliant: Yes
T8100-E-D 制造商:GE Sensing & Inspection Technologies 功能描述:TRANSMITTER, CO2, HUMIDITY, TEMP 制造商:GE MEASUREMENT & CONTROL 功能描述:TRANSMITTER, CO2, HUMIDITY, TEMP; Plug Type:- ;RoHS Compliant: Yes 制造商:GE MEASUREMENT & CONTROL/GE SENSING 功能描述:TRANSMITTER, CO2, HUMIDITY, TEMP; Plug Type:- ;RoHS Compliant: Yes
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。

采購需求

(若只采購一條型號(hào)，填寫一行即可)

發(fā)布成功！您可以繼續(xù)發(fā)布采購。也可以進(jìn)入我的后臺(tái)，查看報(bào)價(jià)

發(fā)布成功！您可以繼續(xù)發(fā)布采購。也可以進(jìn)入我的后臺(tái)，查看報(bào)價(jià)

*型號(hào) *數(shù)量 廠商 批號(hào) 封裝
添加更多采購

我的聯(lián)系方式

*
*
*