參數(shù)資料
型號(hào): T8100A
英文描述: H.100/H.110 Interface and Time-Slot Interchangers
中文描述: H.100/H.110接口和時(shí)隙Interchangers
文件頁(yè)數(shù): 64/112頁(yè)
文件大?。?/td> 1408K
代理商: T8100A
60
Lucent Technologies Inc.
Advance Data Sheet
November 1999
H.100/H.110 Interfaces and Time-Slot Interchangers
Ambassador T8100A, T8102, and T8105
2 Architecture and Functional Descrip-
tion
(continued)
2.6 Interface Section
(continued)
2.6.3 Framing Groups
(continued)
There are two groups of frame pulses. Each frame
group consists of 12 output pins, which are enabled
sequentially after a programmed starting point. The 12
outputs of the frame group are pulsed in sequence,
once every 8 bit times, where the bit time is set by the
rate option. The groups are denoted group A and group
B. This section describes framing group A. Framing
group B is made up of similar registers. A pair of regis-
ters controls each group. Two registers, FRLA and
FRHA, control the spacing of the 12 frame pulses
(rate), their pulse width, polarity, and the offset of the
first pulse from the frame boundary. The FRPL and
FRPH registers are also used in configuring the frame
groups; however, for this discussion they are equal to
zero. With FRPL and FRPH equal to zero, the frame
group A bits [0:11] are output on pins FGA[0:11] and
frame group B bits are routed to group B output pins
FGB[0:11]. FRHA has 5 control bits and 3 upper offset
bits. FRLA has 8 bits for the lower part of the offset.
Thus, the offset is 11 bits. The 11-bit offset corre-
sponds to 2
11
values which allow programming offsets
from 0 ns to 125 μs. Note that the resolution is less
than 1 data bit. For example, if the frame group clock is
programmed to 2.048 MHz, the resolution is 0.125 (one
eighth) of a data bit.
2.6.3.1 Frame Group Timing
The frame boundary is the point where /CT_FRAME is
low and CT_C8 is starting its low-to-high transition.
The offset sets the first output (pin FGA0) relative to
the frame boundary. With a zero offset, the rising edge
of the first frame group is coincident with the first falling
edge of the 8.192 MHz clock, output at the LS_C[3:0]
port, after the start of the frame boundary.
Referring to Figure 28, the rising edges of the
8.192 MHz, 4.096 MHz, and 2.048 MHz clocks are all
coincident and occur in the center of CT_FRAME (not
shown in Figure 28). This is the start of the following:
I
Physical frame.
I
The first data bit of the first time slot on the CT bus
and the local bus.
Because of the complexity of the device and other
design considerations, with a frame group offset of
zero, the first frame pulse starts after 1 bit clock
(1/16.384 MHz) with respect to the start of the frame
boundary.
To have the frame group start at the frame boundary,
the 11-bit offset is all ones (0x7FF). That is, FRLA is
0xFF and the lower 3 bits (bits [2:0]) of FRHA are 1.
The 11-bit offset allows the user to position the starting
frame pulse anywhere within the 125 ms frame. The
frame pulse can be adjusted in increments of 61 ns
(1/16.384 MHz). The control bits in the FRHA register
enable the user to invert the frame group pulse and to
adjust the width of these pulses.
In addition to sequenced pulses, the frame groups can
be used as simple programmed output registers. When
group A is used as a programmed output, the bits are
sent from the FRLA [0x20] and FRHA [0x21] registers.
Bits [0:7] of the programmed output come from bits
[0:7] of FRLA [0x20]. Bits [8:10] of the programmed
output come from the high start (bits [0:2]) of FRHA
[0x21], and bit 11 of the programmed output comes
from the FAI bit (bit 3) of FRHA [0x21]. When group B
is used as a programmed output, bits 0:7 of the output
come from bits 0:7 of separate register FRPL [0x24],
and bits [8:11] of the output come from bits 0:3 of
another register FRPH [0x25]. The upper nibble of
FRPH [0x25] also has output routing functions associ-
ated with it. Register FRPH [0x25] is illustrated in Table
57; see Figure 19 for a diagram of the selection
options.
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