參數(shù)資料
型號(hào)： T8100A
英文描述： H.100/H.110 Interface and Time-Slot Interchangers
中文描述： H.100/H.110接口和時(shí)隙Interchangers
文件頁數(shù)： 12/112頁
文件大小： 1408K
代理商： T8100A
8
Lucent Technologies Inc.
Advance Data Sheet
November 1999
H.100/H.110 Interfaces and Time-Slot Interchangers
Ambassador T8100A, T8102, and T8105
1 Product Overview
(continued)
1.3 Pin Information
(continued)
Table 1. Pin Descriptions: Clocking and Framing Pins
Symbol
L_REF[7:0]
Pin
45—38 P3, N4, R1, P2, N3, M4,
Ball
Type
I
Name/Description
P1, N2
R14
P13
U16
Local Frame Reference Inputs.
50 k
internal pull-up.
/C16+
/C16–
/C4
102
101
104
I/O
H-MVIP16.384 MHz Clock Signals.
Differential
24 mA drive,
Schmitt in, 50 k
internal pull-up.
MVIP4.096 MHz Clock.
8 mA drive, Schmitt in, 50 k
internal
pull-up.
MVIP2.048 MHz Clock.
8 mA drive, Schmitt in, 50 k
internal
pull-up.
SC-Bus 2/4/8 MHz Clock.
24 mA drive, Schmitt in, 50 k
internal
pull-up.
SC-Bus Inverted 4/8 MHz Clock (Active-Low).
24 mA drive,
Schmitt in, 50 k
internal pull-up.
Local Selected Clocks.
1.024 MHz, 2.048 MHz, 4.096 MHz,
8.192 MHz, 16.384 MHz, frame (8 kHz), or secondary (NETREF).
8 mA drive, 3-state.
Frame Group A.
8 mA drive, 3-state.
I/O
C2
106
T17
I/O
SCLK
110
R17
I/O
SCLKX2
108
P15
I/O
L_SC[3:0]
36—33
M3, N1, M2, M1
O
FGA[5:0]
94—99
R12, T13, U14, P12,
R13, T14
T11, P11, R11, U12,
T12, U13
O
FGA[11:6]
87—92
FGB[5:0]
80—85 U9, R9, U10, T10, R10,
U11
O
Frame Group B.
8 mA drive, 3-state.
FGB[11:6]
PRIREFOUT
PLL1V
DD
73—78
58
53
U6, T7, R8, U7, T8, U8
P5
U1
O
—
Output from Primary Clock Selector/Divider.
8 mA drive.
PLL #1 VCO Power.
This pin must be connected to power, even if
PLL #1 is not used.
PLL #1 VCO Ground.
This pin must be connected to ground,
even if PLL #1 is not used.
PLL1GND
51
No ball for this
signal, internally
connected.
T3
—
EN1
55
I
PLL #1 Enable.
Requires cap to V
SS
to form power-on reset, or
may be driven with RESET line. 50 k
internal pull-up.
PLL #1 Rate Multiplier.
Can be 2.048 MHz or 4.096 MHz.
50 k
internal pull-up.
PLL #2 VCO Power.
This pin must be connected to power, even if
PLL #2 is not used.
PLL #2 VCO Ground.
This pin must be connected to ground,
even if PLL #2 is not used.
4MHZIN
54
U2
I
PLL2V
DD
208
A2
—
PLL2GND
206
No ball for this
signal, internally
connected.
C2
—
EN2
3
I
PLL #2 Enable.
Requires cap to V
SS
to form power-on reset, or
may be driven with RESET line. 50 k
internal pull-up.
PLL #2 Rate Multiplier.
Input, 50 k
internal pull-up.
16.384 MHz Crystal Connection or External Clock Input.
16.384 MHz Crystal, Feedback Connection.
Selected output to drive framers. 8 mA drive, 3-state.
Clock Error.
Logical OR of CLKERR register flags (only). 8 mA
drive, 3-state.
System Error.
Logical OR of all CLKERR and SYSERR register
flags. 8 mA drive, 3-state.
3MHZIN
XTALIN
XTALOUT
TCLKOUT
CLKERR
1
A1
R2
T1
C4
E1
I
I
47
48
203
13
O
O
O
SYSERR
12
F3
O
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
T8100A-BAL 制造商:Alcatel-Lucent 功能描述:ELECTRONIC COMPONENT
T8100A-BAL4DB 制造商:AGERE 功能描述:
T8100-D 制造商:GE Sensing & Inspection Technologies 功能描述:CO2/TEMP SENS WALL MNT DUAL OUT
T8100-E 制造商:GE Sensing & Inspection Technologies 功能描述:TRANSMITTER, CO2, HUMIDITY, TEMP 制造商:GE MEASUREMENT & CONTROL 功能描述:TRANSMITTER, CO2, HUMIDITY, TEMP; Plug Type:- ;RoHS Compliant: Yes 制造商:GE MEASUREMENT & CONTROL/GE SENSING 功能描述:TRANSMITTER, CO2, HUMIDITY, TEMP; Plug Type:- ;RoHS Compliant: Yes
T8100-E-D 制造商:GE Sensing & Inspection Technologies 功能描述:TRANSMITTER, CO2, HUMIDITY, TEMP 制造商:GE MEASUREMENT & CONTROL 功能描述:TRANSMITTER, CO2, HUMIDITY, TEMP; Plug Type:- ;RoHS Compliant: Yes 制造商:GE MEASUREMENT & CONTROL/GE SENSING 功能描述:TRANSMITTER, CO2, HUMIDITY, TEMP; Plug Type:- ;RoHS Compliant: Yes
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