參數(shù)資料
型號: T8100A
英文描述: H.100/H.110 Interface and Time-Slot Interchangers
中文描述: H.100/H.110接口和時隙Interchangers
文件頁數(shù): 110/112頁
文件大?。?/td> 1408K
代理商: T8100A
106
Lucent Technologies Inc.
Advance Data Sheet
November 1999
H.100/H.110 Interfaces and Time-Slot Interchangers
Ambassador T8100A, T8102, and T8105
Appendix B. Minimum Delay and Con-
stant Delay Connections
(continued)
B.2 Delay Type Definitions
(continued)
B.2.3 Mixed Minimum/Constant Delay
An interesting mix of delays occurs when the individual
FME bits are overridden and a chip-wide selection for
FME is used. In short, when these devices are placed
in this mode, and when register bits CON[1:0] = 10, for-
ward connections provide minimum delay, reverse con-
nections provide constant delay. When CON[1:0] = 11,
reverse connections provide minimum delay, forward
connections provide constant delay. The latter is inter-
esting because, graphically, the TS
to latency map-
ping appears as a linear monotonic function covering
255 time slots. (Graphs are in the section which fol-
lows.) The latency equations follow:
CON[1:0] = 10:
Forward Connections: L = TS
(3
TS
127).
Reverse Connections: L = 256 + TS
(–127
TS
0).
CON[1:0] = 11:
Forward and Reverse: L = 128 + TS
(–125
TS
127).
Table 83, Table of Special Cases (Exceptions), applies
to the mixed delays in a similar manner. Simply use bit
0 of CON for the FME value in Table 83.
5-6225(F)
Figure 41. Mixed Minimum/Constant Delay Connections, CON[1:0 = 10]
A
(
RESULTING LATENCY
(TIME SLOTS)
–127
0
127
127
256
FME=0
FME=0
0
–127
258
2
2
129
SPECIAL LONG LATENCY
CONNECTIONS
(SEE TEXT)
128
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