參數(shù)資料
型號： T8100A
英文描述： H.100/H.110 Interface and Time-Slot Interchangers
中文描述： H.100/H.110接口和時隙Interchangers
文件頁數(shù)： 58/112頁
文件大小： 1408K
代理商： T8100A
54
Lucent Technologies Inc.
Advance Data Sheet
November 1999
H.100/H.110 Interfaces and Time-Slot Interchangers
Ambassador T8100A, T8102, and T8105
2 Architecture and Functional Descrip-
tion
(continued)
2.5 Clocking Section
(continued)
2.5.8 Clock Control Register Definitions
(continued)
2.5.8.1 Basic Fallback Mode
Note:
The fallback mechanism is sticky in that the
device will not fallback again if the clocks which
were used for fallback fail.
The four modes are described below.
FTS 00
The resource multiplexer is bypassed, thus
selection of this mode of operation assumes
that PLL #1 has been set up for a x16 multiply
(in CKR). The PLL selection cannot be
changed during fallback, so both primary and
secondary choices must supply the same fre-
quency into PLL #1. Thus, in the case of FTS =
00, it is assumed that the primary clock selec-
tion has been set up for 4.096 MHz.
FTS 01
The secondary selections will be ignored. The
clock error registers will continue to report tran-
sient and stuck errors (if unmasked by CKW),
but will not induce the fallback sequence.
There are three reasons to use this: as an aid
in initializing the T8100, as a diagnostic tool, or
in a software-only fallback system. This last
item requires some additional explanation.
There is a provision in the ECTF H.100 and
H.110 specifications which provide for a piece
of hardware to support both hardware and soft-
ware based fallback. In the software-only
selection, the part must still report clock fail-
ures. This is accomplished through the CLK-
ERR pin, which provides the interrupt to the
host, and CLKERR1, CLKERR2, CLKERR3,
and CKW, which provide the details of the fail-
ures. An interrupt will thus trigger a software
sequence which will reprogram the clocks. In
the hardware based fallback, the selection is
automatic with the intent of maintaining stable
operation until the software can service the
device.
FTS 10
The choice to move into fallback is triggered by
an error on the main (primary) clock selection,
as defined by the lower 4 bits of CKM. The
main clock selection will have as few as one
signal associated with it (main clock selection =
NETREF) or as many as five (main clock
selection = H-MVIP which is /C16+, /C16-, /C4,
C2, and /FR_COMP). Thus, a failure on any
clock in the main selection will induce fall-
back. Note that these signals
must
be
unmasked, as well. So in the case of
NETREF above, the lowest bit of CKW must be
set. In the case of H-MVIP at least bits 3, 4,
and 5 must be set in CKW. Any additional
CKW bits which are set (but not required) will
flag a failure on the CLKERR pin and will be
set in the CLKERR registers but will not induce
a fallback. Further, if fallback is initiated, the
CLKERR and the SYSERR pins will go high.
The fallback will occur to the selections made
in the CKS register. One additional note: this
does not apply to the local reference inputs
(selections 1000—1111 in the lower 4 bits of
CKM). Since these typically come from fram-
ers or HDLC controllers, these devices have
their own error reporting systems.
FTS 11
This selection induces fallback on the failure of
either the A or B clocks independent of the
main clock selection. (A and B must be
unmasked in CKW.) Since this is intended for
H.100 and H.110, it would be unwise to pro-
gram the main selection to be anything other
than A clocks or B clocks. For H.100, the FTS
= 11 selection also enables a state machine
which controls the compatibility clocks. If bit 5
has been set in the primary clock programming
and is also programmed to drive either the A or
B clocks, then a self-detected failure will cause
the T8100 to remove its clocks from the H.100
bus, both its main (A or B clock set) and the
compatibility clocks. Likewise, if bit 5 was not
set in the primary clock programming and if the
part is slaving to one set (A or B) and driving
the other (B or A, respectively) then a failure
detected on the clock it is slaving to will auto-
matically cause the device to drive the compat-
ibility clocks. In this way, an H.100 system with
an A and B clock set can maintain the opera-
tion of compatibility clocks in addition to main-
taining H.100 clocking.
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