參數(shù)資料
型號: T8100A
英文描述: H.100/H.110 Interface and Time-Slot Interchangers
中文描述: H.100/H.110接口和時隙Interchangers
文件頁數(shù): 44/112頁
文件大?。?/td> 1408K
代理商: T8100A
40
Lucent Technologies Inc.
Advance Data Sheet
November 1999
H.100/H.110 Interfaces and Time-Slot Interchangers
Ambassador T8100A, T8102, and T8105
2 Architecture and Functional Descrip-
tion
(continued)
2.4 Subrate Switching for the Ambassador
Family
(continued)
2.4.4 Using the Existing Architecture
It is possible to create a subrate switching structure uti-
lizing a variant of the existing pipelined multistream
CAM architecture. Since access to the H-bus continues
to require bytes, the CAM size does not change. CAMs
will continue to track stream and time-slot addresses.
The changes to the architecture are all related to the
data storage as it comes in from the bus. The most fun-
damental change is that selected subrate data pieces
can be individually stored, not necessarily the entire
incoming data byte. For example, the uppermost dibit
can be stored and the other dibits ignored. Thus, with
several incoming data bytes contributing subrate
pieces, a new data byte, composed of one or more
subrate pieces from different sources, can be con-
structed. (See Figure 12.)
Structurally, the change in the data buffers is from the
existing 512 x 8 (T8102, T8105 only) register file (or
256 x 8 for the T8100A) to eight 512 x 1 (T8102, T8105
only) register files (or eight 256 x 1 register files). Each
of these columns has a separate write enable. To sup-
port this change, the tag register associated with each
CAM must be extended by 7 bits to identify the source
of the subrate data (i.e., identify which piece of the
incoming byte is to be used) and the destination of the
subrate data (i.e., identify which bits of the data loca-
tion will be written into). Table 45 Permitted Tag Exten-
sions below lists the permitted entries in the extension
of the tag. While the writes into the data buffers are fine
grained, as small as a single bit write, the reads must
be as a whole byte to maintain the byte-orientation of
the H.100/H.110 bus as described previously.
Table 45. Permitted Tag Extensions
The subrate switching is optional; a bit in the identifica-
tion register will permit the subrate operation. The bit
defaults to zero, so that the tag extension is ignored
and the data buffers are treated as 512 x 8 (T8102,
T8105 only). If set, the columns are individually
addressed by the tag extensions.
Tag
Extensions
Bit
6
5
4
3
2
Destination
Field
00x
1
0
MSB
Source
Field
00x
Byte
(1 entry only)
Nibble
(4 combinations)
Dibit
(16 combinations)
Bit
(64 combinations)
0
0
010—011
010—011
0
100—111
100—111
1
000—111
000—111
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