參數(shù)資料
型號(hào)： TLV320AIC36IZQE
廠商： TEXAS INSTRUMENTS INC
元件分類： 消費(fèi)家電
英文描述： SPECIALTY CONSUMER CIRCUIT, PBGA80
封裝： 5 X 5 MM, GREEN, PLASTIC, VFBGA-80
文件頁數(shù)： 102/165頁
文件大小： 1895K
代理商： TLV320AIC36IZQE
www.ti.com
SBAS387A – MAY 2009 – REVISED JUNE 2010
5.10 ADC Setup
The following discussion is intended to guide a system designer through the steps necessary to configure
the TLV320AIC36 ADC.
Step 1
The system clock source (master clock) and the targeted ADC sampling frequency must be identified.
Depending on the targeted performance, the decimation filter type (A, B, or C) and OSR value can be
determined.
Filter A with AOSR of 128 or 64 should be used for 48-kHz (or below) high-performance operation. An
AOSR of 64 can be also used for 96-kHz operation
Filter B with AOSR of 64 should be used for 96-kHz operations.
Filter C with AOSR of 32 should be used for 192-kHz operations
Based on the identified filter type and the required signal processing capabilities the appropriate
processing block can be determined from the list of available processing blocks (PRB_R1 to PRB_R18)
(see Table 5-4).
Based on the available master clock, the chosen OSR and the targeted sampling rate, the clock divider
values NADC and MADC can be determined. If necessary the internal PLL will add a large degree of
flexibility.
In summary, Codec_Clkin which is either derived directly from the system clock source or from the internal
PLL, divided by MADC, NADC and AOSR, must be equal to the ADC sampling rate ADC_FS. The
Clodec_Clkin clock signal is shared with the DAC clock generation block.
CODEC_CLKIN = NADC*MADC*AOSR*ADC_FS
To a large degree NADC and MADC can be chosen independently in the range of 1 to 128. In general
NADC should be as large as possible as long as the following condition can still be met:
MADC*AOSR/32
≥ RC
RC is a function of the chosen processing block and is listed in the Table 5-4.
At this point the following device specific parameters are known:
PRB_Rx, AOSR, NADC, MADC, common mode setting
Additionally if the PLL is used the PLL parameters P, J, D, and R are determined as well.
Copyright 2009–2010, Texas Instruments Incorporated
APPLICATION INFORMATION
41
Product Folder Link(s): TLV320AIC36
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