參數(shù)資料
型號: TLV320AIC36IZQE
廠商: TEXAS INSTRUMENTS INC
元件分類: 消費(fèi)家電
英文描述: SPECIALTY CONSUMER CIRCUIT, PBGA80
封裝: 5 X 5 MM, GREEN, PLASTIC, VFBGA-80
文件頁數(shù): 129/165頁
文件大?。?/td> 1895K
代理商: TLV320AIC36IZQE
LD(n)
LD (n+1)
BIT
CLOCK
DATA
-
1
-
2
-
3
2
1
0
3
-
1
-
2
-
3
0
3
2
1
-
1
-
2
N N N
-
3
RD(n)
WORD
CLOCK
LEFT CHANNEL
RIGHT CHANNEL
LD(n)=n'thsampleofleftchanneldata
RD(n)=n'thsampleofrightchanneldata
LD(n)
LD(n+1)
BIT
CLOCK
DATA
-
1
-
2
-
3
2
1
0
3
-
1
-
2
-
3
0
3
2
1
-
1
-
2
N N N
-
3
RD(n)
WORD
CLOCK
LEFT CHANNEL
RIGHT CHANNEL
LD(n)=n'thsampleofleftchanneldata
RD(n)=n'thsampleofrightchanneldata
LD(n)
LD (n+1)
BIT
CLOCK
DATA
N
-
1
N
-
2
N
-
3
2
1
0
3
N
-
1
N
-
2
N
-
3
0
3
2
1
N
-
1
N
-
2
N
-
3
RD(n)
WORD
CLOCK
LEFT CHANNEL
RIGHT CHANNEL
SBAS387A – MAY 2009 – REVISED JUNE 2010
www.ti.com
Figure 5-42. Timing Diagram for DSP Mode
Figure 5-43. Timing Diagram for DSP Mode With Offset = 1
Figure 5-44. Timing Diagram for DSP Mode With Offset = 1 and Bit Clock Inverted
For DSP mode, the number of bit-clocks per frame should be greater than twice the programmed
word-length of the data. Also the programmed offset value should be less than the number of bit-clocks
per frame by at least the programmed word-length of the data.
5.17.1.5 Secondary I2S
The audio serial interface on the TLV320AIC36 has an extensive I/O control to allow communication with
two independent processors for audio data. Each processor can communicate with the device one at a
time. This feature is enabled by register programming of the various pin selections.
Figure 5-45 illustrates possible audio interface routing.
66
APPLICATION INFORMATION
Copyright 2009–2010, Texas Instruments Incorporated
Product Folder Link(s): TLV320AIC36
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