參數(shù)資料
型號： TLV320AIC36IZQE
廠商： TEXAS INSTRUMENTS INC
元件分類： 消費家電
英文描述： SPECIALTY CONSUMER CIRCUIT, PBGA80
封裝： 5 X 5 MM, GREEN, PLASTIC, VFBGA-80
文件頁數(shù)： 112/165頁
文件大小： 1895K
代理商： TLV320AIC36IZQE
SBAS387A – MAY 2009 – REVISED JUNE 2010
www.ti.com
Table 5-17. DAC Interpolation Filter C, Specification
Parameter
Condition
Value (Typical)
Units
Filter gain pass band
0 … 0.35 Fs
±0.03
dB
Filter gain stop band
0.60 … 1.4 Fs
–43
dB
Filter group delay
13/Fs
s
5.12 DAC Output Drivers
5.12.1 Analog Fully Differential Line Output Drivers
The TLV320AIC36 has two fully differential line output drivers, each capable of driving a 10k
differential
load. Each driver can connect to the left or the right DAC, the left or the right ADC PGA output, the left or
right line input, or any combination of the six. The design includes extensive capability to adjust signal
levels independently before any mixing occurs, beyond that already provided by the PGA gain and the
DAC digital volume control. Note that since both left and right channel signals are routed to all output
drivers, a mono mix of any of the stereo signals can easily be obtained by setting the volume controls of
both left and right channel signals to –6 dB and mixing them. Undesired signals can also be disconnected
from the mix as well through register control.
The TLV320AIC36 includes an output level control on each output driver with limited gain adjustment from
0 dB to +9 dB. The output driver circuitry in this device are designed to provide a low distortion output
while playing full-scale stereo DAC signals at a 0 dB gain setting. However, a higher amplitude output can
be obtained at the cost of increased signal distortion at the output. This output level control allows the user
to make this tradeoff based on the requirements of the end equipment. Note that this output level control
is not intended to be used as a standard output volume control. It is expected to be used only sparingly for
level setting, that is, adjustment of the full-scale output range of the device.
Each differential line output driver can be powered down independently of the others when it is not needed
in the system. When placed into powerdown through register programming, the driver output pins will be
placed into a high-Z, high-impedance state.
The signal routing for the line level drivers is configured using Page 2, Registers 80 through 93
5.12.2 Analog High-Power Output Drivers
The TLV320AIC36 includes four single-ended high power output drivers arranged as two stereo pairs.
These output drivers are capable of driving 0.89 Vrms each into a 16-
load if one pair is enabled or 0.5
Vrms each into 16-
if both pairs are enabled. The volume control and mixing blocks for the high-power
output drivers are effectively identical to those of the line-level drivers. Note that each of these drivers
have a output level control block like those included with the line output drivers, allowing gain adjustment
up to +9 dB on the output signal. As in the previous case, this output level adjustment is not intended to
be used as a standard volume control, but instead is included for additional full-scale output signal level
control. In order to drive 0.89 Vrms for a full-scale DAC output into the load, the output level adjustment
must be set to +2 dB.
The high power output drivers include additional circuitry to avoid artifacts on the audio output during
power-on and power-off transient conditions. The power-up delay time for the high power output drivers is
programmable over a wide range of time delays, from instantaneous up to 4-sec, using Page-2/Reg-42.
When these output drivers are powered down, they can be placed into a variety of output conditions based
on register programming. If lowest power operation is desired, then the outputs can be placed into a
tri-state condition, and all power to the output stage is removed. However, this generally results in the
output nodes drifting to rest near the upper or lower analog supply, due to small leakage currents at the
pins. This then results in a longer delay requirement to avoid output artifacts during driver power-on. In
order to reduce this required power-on delay, the TLV320AIC36 includes an option for the output pins of
the drivers to be weakly driven to the AGND level they would normally rest at when powered with no
signal applied.
50
APPLICATION INFORMATION
Copyright 2009–2010, Texas Instruments Incorporated
Product Folder Link(s): TLV320AIC36
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相關代理商/技術參數(shù)
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