參數(shù)資料
型號： TLV320AIC36IZQE
廠商： TEXAS INSTRUMENTS INC
元件分類： 消費家電
英文描述： SPECIALTY CONSUMER CIRCUIT, PBGA80
封裝： 5 X 5 MM, GREEN, PLASTIC, VFBGA-80
文件頁數(shù)： 140/165頁
文件大小： 1895K
代理商： TLV320AIC36IZQE
SBAS387A – MAY 2009 – REVISED JUNE 2010
www.ti.com
ratio for digital filter =4, only used for custom filters #w 30 16 04 # CODEC INTERFACE,
DIGITAL ADC,DAC CONTROLS, INCLUDES ANALOG DAC,ADC POWERUP
############################################################ # I2S, 24bit wordlength (19=2x) ,
16bit (19=0x), BCLK, WCLK are outputs (19=xC), inputs (19=x0) w 30 19 20 # DAC filter engine 1
w 30 3C 01 # ADC filter engine 1 w 30 3D 01 # Left, Right ADC not muted digital gain=0 dB
(52=00), gain=-0.1 dB (52=11) w 30 52 00 # ADCL, ADCR digital gain (7b signed 0.5 dB steps) w
30 53 00 w 30 54 00 # L AGC, R AGC disabled, target=-5.5 dB w 30 56 00 w 30 5E 00 #
PRI_BCLK_OUT=internally generated BCLK, SEC_BCLK_OUT=Primary BCLK, # PRI_WCLK_OUT= ADC_FS
clock, SEC_WCLK=Primary WCLK, PRI_DOUT=DOUT from CODEC w 30 21 10 # ADC filter output to I2S,
I2S to DAC filter input, BCLK not inverted, BCLK WCLK active even when CODEC is PD w 30 1B 06 #
LADC,RADC powerup, DIG_MIC_INP, LDIG_MIC,RDIG_MIC disabled, soft-step disabled w 30 00 00 w 30
51 C2 # LDAC,RDAC powerup,soft-step disble, left data to LDAC, right data to RDAC (d6), L->R, R-
>L (ea), L->L, L->R (da) w 30 3F d6 # Dac auto-mute disable, left,right dac not muted,
left,right dac volume control independent w 30 40 00 # LDAC, RDAC digital gain 8 bit signed
(0.5 dB steps) -6 dB (41=f4,42=f4) w 30 41 00 w 30 42 00 # ANALOG ADC CODE
################################### # Briefly connect internal CM to LEFT and RIGHT MIC PGA #
for CM startup in differential mode w 30 00 01 w 30 34 00 w 30 36 80 w 30 37 00 w 30 39 80 #
connect mic1p,1m to pga leftp (34=20) leftm (36=20) 20k # connect mic2p,2m to pga rightp
(37=20) rightm (39=20) 20k # connect extmic_p,m to pga leftp (34=08) leftm (36=08) 20k #
connect lineinl to pgalp (34=80), cml to pgalm (36=80) # connect lineinr to pgarp (37=80), cmr
to pgarm (39=80) w 30 00 01 w 30 34 20 w 30 36 20 w 30 37 20 w 30 39 20 # all inputs float if
not used (3A=00), all inputs are connected to CM if not used (3A=FF) w 30 3A 00 # LADC,RADC
analog PGA gain=0 dB (0.5 dB steps), w 30 3B 00 w 30 3C 00 # ADC CM=0.9V (0A=00), 0.75V (0A=40)
w 30 0A 00 # select LINE2L, LINE2R, 28=14 SE in bypass amp w 30 00 02 w 30 28 14 # Modulator
start-up sequence w 30 00 fd w 30 0d 0d w 30 04 20 w 30 0d 00 # ANALOG DAC CODE
################################### # dacl,dacr power up, short ckt protect output drivers
enabled # c0=both dacs, 80=ldac, 40=rdac w 30 00 02 w 30 25 c0 w 30 26 02 # BCLK powerup,
divide 4 w 30 00 00 w 30 1C 84 # pop reduction for DAC output drivers w 30 00 02 w 30 2A 34 #
enable outputs and set gains # HPR 2D-33 # HPL 34-3a # RECL 3b-41 # RECR 42-48 # LOL 50-56 #
LOR 57-5D # disable ground sense for hpr, hpl (24=00) w 30 00 02 w 30 24 00 #enable HPR gain=0,
#connect to LINEL (2d) PGAL(2e) DACL (2f) LINER (30) PGAR (31) DACR (32), 80=0 dB f5=-78 dB,
f6=mute w 30 00 02 w 30 2f 80 w 30 33 09 #enable HPL gain=0 # connect to LINEL (34) PGAL (35)
DACL (36) LINER (37) PGAR (38) DACR (39), 0 dB w 30 39 80 w 30 3a 09 # enable recl gain=0 #
connect to LINE2L (3B) PGAL (3C) DACL (3D) LINE2R (3E) PGAR (3F) DACR (40) # a.0 0d=03 a.1
(comment out) w 30 00 02 w 3
0 3d 80 w 30 41 00 # enable recr gain=0 # connect to LINE2L (42) PGAL (43) DACL (44) LINE2R
(45) PGAR (46) DACR (47) w 30 47 80 w 30 48 00 #enable LOL (09) gain=0 #connect to LINE2L (50)
PGAL (51) DACL (52) LINE2R (53) PGAR (54) DACR (55), 80=0 dB f5=-78 dB w 30 00 02 w 30 52 80 w
30 56 09 #enable LOR gain=0 #connect to LINE2L (57) PGAL (58) DACL (59) LINE2R (5a) PGAR (5b)
DACR (5c), att=0 dB w 30 5c 80 w 30 5D 09 # reduce hp,dac,lo,rec currents to lowest power state
w 30 00 02 w 30 7a 55 # set modulator taps for best performance (0,2,4,6,8,a or 0,1,2,3,4,5 or
1,1,1,1,1 or 0,3,5,7,9,c) w 30 00 00 w 30 72 30 w 30 73 75 w 30 74 c9 # dac current control
1.5x current (6B=40), 0.5x current (6B=80) w 30 00 02 w 30 6B 00
5.21 Detailed Application Example – Low Power Modes
############################################################ # Example script for the ADC and
DAC data paths - low and ultra low power modes # dac to hp only for lowest power # Assumes
Mclk(input)=11.2896 MHz, Wclk(input) =fs=44.1kHz, Bclk(input)=2.8224 MHz # I2S data, 24bits,
BCLK, WCLk are inputs # HPR, HPL are single ended headphone outputs # # ultra low power mode
(search ulp:) # low power (search lp:) # adc on (search adc on:)
############################################################ # software reset w 30 00 00 w 30
01 01 w 30 01 00 # PMU CODE ############################################################ #
charge pump on with slow clocks(71=00 disabled, 71=01 clk=BCLK, 72=73=0b Bclk/6) w 30 00 02 w
30 72 7f w 30 73 7f w 30 71 01 # turn on ADC ,DAC LDO (74=00), no current limit (76=00), #
short ckt protect, ADC=1.75V, LDO BGAP=on (77=00) # DAC=+-1.75 (78=33), +-1.65 (78=22), +-1.5
(78=11), +-1.4 (78=00) # ulp: 74=07 78=00, lp: 74=00 78=11, normal 74=00,78=22 w 30 00 02 w 30
74 00 w 30 76 00 w 30 77 00 w 30 78 11 # CLOCK CODE
############################################################ # clocking settup, see fig. 5-33
clock dist tree # no pll: 04=00,05=00,0b=81,12=81 # pll: 04=08,05=91,0b=88,12=88 #
CODEC_CLKIN=PLL_CLK, PLL_CLKIN=MCLK_PIN (04=08) w 30 00 00 w 30 04 00 # PLL power up, P = 1
(divide), R=1 (mult) # PLL off 05 =00 w 30 05 00 # PLL multiply 8.0000 w 30 06 08 w 30 07 00 w
30 08 00 # DAC CLOCK CODE ############################################################ # NDAC
power up and div by 1 (88) (max divide 80 =128, a0=32) w 30 0B 81 # MDAC power up and div by 2
(82) (max divide 80=128) w 30 0C 82 # DAC OSR=128 (0E=80) w 30 0D 00 w 30 0E 80 # DAC Mac
instructions per FS=256 (40) w 30 0F 40 # DAC inter ratio=8 w 30 10 08 # ADC CLOCK CODE
############################################################ # NADC power up and div by 1 w 30
12 81 # MADC power up and div by 2 (82) w 30 13 82 # ADC OSR=128 w 30 14 80 # ADC MAC
instructions per FS=94 w 30 15 5E # ADC dec ratio=4 w 30 16 04 # CODEC INTERFACE, DIGITAL
ADC,DAC CONTROLS, INCLUDES ANALOG DAC,ADC POWERUP
############################################################ # I2S, 24bit wordlength (2) ,
BCLK, WCLK are outputs (C), inputs (0) w 30 19 20 # DAC filter engine 1, 8x inter, 3 biquads
(3c=01), # ulp: 3c=11, lp: 3c=11 w 30 3C 11 # ADC filter engine 1, 4x dec, 1st order IIR w 30
76
APPLICATION INFORMATION
Copyright 2009–2010, Texas Instruments Incorporated
Product Folder Link(s): TLV320AIC36
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TLV320AIC36IZQER 功能描述:接口—CODEC Low Pwr Stereo Aud Codec RoHS:否 制造商:Texas Instruments 類型: 分辨率: 轉(zhuǎn)換速率:48 kSPs 接口類型:I2C ADC 數(shù)量:2 DAC 數(shù)量:4 工作電源電壓:1.8 V, 2.1 V, 2.3 V to 5.5 V 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:DSBGA-81 封裝:Reel
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