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參數(shù)資料
| 型號(hào)： | TLV320AIC36IZQE |
| 廠商： | TEXAS INSTRUMENTS INC |
| 元件分類： | 消費(fèi)家電 |
| 英文描述： | SPECIALTY CONSUMER CIRCUIT, PBGA80 |
| 封裝： | 5 X 5 MM, GREEN, PLASTIC, VFBGA-80 |
| 文件頁數(shù)： | 83/165頁 |
| 文件大?。?/td> | 1895K |
| 代理商： | TLV320AIC36IZQE |
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Analog
In
Input
Selection
AnalogGain
ADC
PGA
Digital
Volume
Control
DigitalGain
Adjust
Frequency
Response/
Gain
ADC
Filtering
Audio
Interface
+6, 0, -6 dB
0...47.5 dB
Step = 0.5 dB
-12 .. 20 dB
Step = 0.5 dB
0 .. -0.4 dB
Step = 0.1 dB
Fully
Programmable
Coefficients
SBAS387A – MAY 2009 – REVISED JUNE 2010
www.ti.com
In most applications, high-input impedance is desired for analog inputs. However when used with high
gain, as in the case of microphone inputs, the higher-input impedance results in higher noise or lower
dynamic range. The TLV320AIC36 gives the user the flexibility of choosing the input impedance from
10k
, 20k and 40k. When multiple inputs are mixed together, by choosing different input impedances,
level adjustment can be achieved. For example, if one input is selected with 10k
input impedance and
the second input is selected with 20k
input impedance, then the second input is attenuated by half as
compared to the first input. This input level control is intended to be a volume control, but instead used for
level setting.
Mixing of multiple inputs can easily lead to PGA outputs that exceed the range of the internal amplifiers,
resulting in saturation and clipping of the mixed output signal. Whenever mixing is being implemented, the
system designer is advised to take adequate precautions to avoid such a saturation from occurring. In
general, the mixed (summed) signal should not exceed 0 dB.
Typically, voice or audio signal inputs are capacitively coupled to the device. This allows the device to
independently set the common mode of the input signals to values chosen by register control of Page 1,
Register 10, D(6) to either 0.9 V or 0.75 V. The correct value maximizes the dynamic range across the
entire analog-supply range. Failure to capacitively connect the input to the device can cause high offset
due to mismatch in source common-mode and device common-mode setting. In extreme cases it could
also saturate the analog channel, causing distortion.
5.7
ADC Gain Setting
When the gain of the ADC channel is kept at 6 dB and the common mode is set to 0.75 V, a single-ended
input of 0.375 VRMS results in a full-scale digital signal at the output of ADC channel. Similarly, when the
gain is kept at 6 dB, and common mode is set to 0.9 V, a single-ended input of 0.5 VRMS results in a
full-scale digital signal at the output of the ADC channel. However various block functions control the gain
through the channel. The gain applied by the PGA is described in Table 5-1. Additionally, the digital
volume control adjusts the gain through the channel, as described in Section 5.7.2. A finer level of gain is
controlled by fine gain control, as described in Section 5.7.3. The decimation filters A, B, and C along with
the delta-sigma modulator contribute to a DC gain of 1.0 through the channel.
5.7.1
Analog PGA
The TLV320AIC36 features a built-in low-noise PGA for boosting low-level signals, such as direct
microphone inputs, to full-scale to achieve high SNR. This PGA can provide a gain in the range of 0 dB to
47.5 dB for single-ended inputs or 6 dB to 53.5 dB for fully differential inputs (gain calculated with respect
to input impedance setting of 10k
; 20k input impedance will result in 6 dB lower and 40k will result in
12 dB lower gain). This gain can be user controlled by writing to Page 1, Register 59 and Page 1, Register
60. In the AGC mode this gain can also be automatically controlled by the built-in hardware AGC.
24
APPLICATION INFORMATION
Copyright 2009–2010, Texas Instruments Incorporated
Product Folder Link(s): TLV320AIC36
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