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參數(shù)資料
| 型號(hào)： | TLV320AIC36IZQE |
| 廠商： | TEXAS INSTRUMENTS INC |
| 元件分類： | 消費(fèi)家電 |
| 英文描述： | SPECIALTY CONSUMER CIRCUIT, PBGA80 |
| 封裝： | 5 X 5 MM, GREEN, PLASTIC, VFBGA-80 |
| 文件頁數(shù)： | 125/165頁 |
| 文件大?。?/td> | 1895K |
| 代理商： | TLV320AIC36IZQE |
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SBAS387A – MAY 2009 – REVISED JUNE 2010
www.ti.com
Table 5-21. PLL Example Configurations
Fs = 44.1 kHz
MCLK (MHz)
PLLP
PLLR
PLLJ
PLLD
MADC
NADC
AOSR
MDAC
NDAC
DOSR
2.8224
1
3
10
0
3
5
128
3
5
128
5.6448
1
3
5
0
3
5
128
3
5
128
12
1
7
560
3
5
128
3
5
128
13
1
2
4
2336
13
3
64
4
6
104
16
1
5
2920
3
5
128
3
5
128
19.2
1
4
4100
3
5
128
3
5
128
48
4
1
7
560
3
5
128
3
5
128
Fs = 48 kHz
2.048
1
3
14
0
2
7
128
7
2
128
3.072
1
4
7
0
2
7
128
7
2
128
4.096
1
3
7
0
2
7
128
7
2
128
6.144
1
2
7
0
2
7
128
7
2
128
8.192
1
4
3
0
2
8
128
4
128
12
1
7
1680
2
7
128
7
2
128
16
1
5
3760
2
7
128
7
2
128
19.2
1
4
4800
2
7
128
7
2
128
48
4
1
7
1680
2
7
128
7
2
128
5.17 Interface
5.17.1 Audio Digital I/O Interface
Audio data is transferred between the host processor and the TLV320AIC36 through the digital audio data
serial interface, or audio bus. The audio bus on this device is very flexible, including left or right-justified
data options, support for I2S or PCM protocols, programmable data length options, a TDM mode for
multichannel operation, very flexible master/slave configurability for each bus clock line, and the ability to
communicate with multiple devices within a system directly.
The audio bus of the TLV320AIC36 can be configured for left or right-justified, I2S, DSP, or TDM modes of
operation, where communication with standard telephony PCM interfaces is supported within the TDM
mode. These modes are all MSB-first, with data width programmable as 16, 20, 24, or 32 bits by
configuring Page 0, Register 25, D(5:4). In addition, the word clock and bit clock can be independently
configured in either Master or Slave mode, for flexible connectivity to a wide variety of processors. The
word clock is used to define the beginning of a frame, and may be programmed as either a pulse or a
square-wave signal. The frequency of this clock corresponds to the maximum of the selected ADC and
DAC sampling frequencies.
The bit clock is used to clock in and clock out the digital audio data across the serial bus. When in Master
mode, this signal can be programmed to generate variable clock pulses by controlling the bit-clock divider
in Page 0, Register 28 (see Figure 5-32). The number of bit-clock pulses in a frame may need adjustment
to accommodate various word-lengths as well as to support the case when multiple TLV320AIC36s may
share the same audio bus.
The TLV320AIC36 also includes a feature to offset the position of start of data transfer with respect to the
word-clock. This offset can be controlled in terms of number of bit-clocks and can be programmed in Page
0, Register 26.
The TLV320AIC36 also has the feature of inverting the polarity of the bit-clock used for transferring the
audio data as compared to the default clock polarity used. This feature can be used independently of the
mode of audio interface chosen. This can be configured using Page 0, Register 27, D(3).
62
APPLICATION INFORMATION
Copyright 2009–2010, Texas Instruments Incorporated
Product Folder Link(s): TLV320AIC36
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| TLV320AIC36IZQER | 功能描述:接口—CODEC Low Pwr Stereo Aud Codec RoHS:否 制造商:Texas Instruments 類型: 分辨率: 轉(zhuǎn)換速率:48 kSPs 接口類型:I2C ADC 數(shù)量:2 DAC 數(shù)量:4 工作電源電壓:1.8 V, 2.1 V, 2.3 V to 5.5 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:DSBGA-81 封裝:Reel |
| TLV320ALC23 | 制造商:TI 制造商全稱:Texas Instruments 功能描述:Evaluation Platform for the TLV320ALC23 Stereo Audio CODEC and TLV230DAC23 Stereo DAC |
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| TLV320DA26IRHBG4 | 功能描述:音頻數(shù)/模轉(zhuǎn)換器 IC Lo-Pwr Ster DAC w/Hdphn/Spkr Amp RoHS:否 制造商:Texas Instruments 轉(zhuǎn)換器數(shù)量: 分辨率:16 bit 接口類型:I2S, UBS 轉(zhuǎn)換速率: 信噪比:98 dB 工作電源電壓:5 V DAC 輸出端數(shù)量:2 工作溫度范圍:- 25 C to + 85 C 電源電流:23 mA 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:TQFP-32 封裝:Reel |
| TLV320DAC23 | 制造商:TI 制造商全稱:Texas Instruments 功能描述:STEREO AUDIO D/A CONVERTER, 8-TO 96KHZ WITH INTERGRATED HEADPHONE AMPLIFIER |
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