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參數(shù)資料
| 型號(hào)： | TLV320AIC36IZQE |
| 廠商： | TEXAS INSTRUMENTS INC |
| 元件分類： | 消費(fèi)家電 |
| 英文描述： | SPECIALTY CONSUMER CIRCUIT, PBGA80 |
| 封裝： | 5 X 5 MM, GREEN, PLASTIC, VFBGA-80 |
| 文件頁(yè)數(shù)： | 116/165頁(yè) |
| 文件大?。?/td> | 1895K |
| 代理商： | TLV320AIC36IZQE |
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SBAS387A – MAY 2009 – REVISED JUNE 2010
www.ti.com
5.14 DAC Special Functions
5.14.1 Beep Generation
A special function has also been included in the processing block PRB_P25 for generating a digital
sine-wave signal that is sent to the DAC. This is intended for generating key-click sounds for user
feedback. A default value for the sine-wave frequency, sine burst length, and signal magnitude is kept in
the Tone Generator Registers Page 0, Registers 71 through 79. The sine wave generator is very flexible,
and is completely register programmable using nine registers of 8-bits each to provide many different
sounds.
Two registers are used for programming the 16-bit, twos complement, sine-wave coefficient (Page 0,
Registers 76 and 77). Two other registers program the 16-bit, twos complement, cosine-wave coefficient
(Page 0, Registers 78 and 79). This coefficient resolution allows virtually any frequency of sine wave in the
audio band to be generated up to DAC_FS/2.
Three registers are used to control the length of the sine burst waveform which are located on Page 0,
Registers 73, 74, and 75. The resolution (bit) in the registers of the sine burst length is one sample period,
so this allows great control on the overall time of the sine burst waveform. This 24-bit length timer
supports 16,777,215 sample periods. (For example if DAC_FS is set at 48 kHz, and the registers
combined value equals 96000d (01770h), then the sine burst would last exactly two seconds.)
Two registers are used to independently control the Left sine-wave volume and the Right sine-wave
volume. The 6-bit digital volume control allows level control of 0 dB to –63 dB in one dB steps. The
left-channel volume is controlled by writing to Page 0, Register 71, D(5:0). The right-channel volume is
controlled by Page 0, Register 72, D(5:0). A master volume control for the left and right channel of the
beep generator can be set up using Page 0, Register 72, D(7:6). The default volume control setting is 0
dB, the tone generator maximum-output level.
For playing back the sine wave, the DAC must be configured with regards to clock setup and routing. The
sine wave gets started by setting the Beep Generator Enable Bit (Page 1, Register 71, D(7)=1)). After the
sine wave has played for its predefined time period this bit will automatically set back to 0. While the sine
wave is playing, the parameters of the beep generator cannot be changed. To stop the sine wave while it
is playing set the Beep Generator Enable Bit to 0.
5.14.2 Digital Auto Mute
The TLV320AIC36 also incorporates a special feature, in which the DAC channel is auto-muted when a
continuous stream of DC-input is detected. By default, this feature is disabled. It can be enabled by writing
a non-000 value into Page 0, Register 64, D(6:4). The non-zero value controls the duration of continuous
stream of DC-input before which the auto-mute feature takes effect. This feature is especially helpful for
eliminating high-frequency-noise power being delivered into the load even during silent periods of speech
or music.
5.14.3 Adaptive Filtering
When the DAC is running, the user-programmable filter coefficients are locked and cannot be accessed
for either read or write.
However the TLV320AIC36 offers an adaptive filter mode as well. Setting Register Page 8, Reg 1, D(2)=1
will turn on double buffering of the coefficients. In this mode, filter coefficients can be updated through the
host, and activated without stopping and restarting the DAC. This enables advanced adaptive filtering
applications.
In the double-buffering scheme, all coefficients are stored in two buffers (Buffers A and B). When the DAC
is running and adaptive filtering mode is turned on, setting the control bit Page 8, Register 1, D(0)=1
switches the coefficient buffers at the next start of a sampling period. This bit is set back to 0 after the
switch occurs. At the same time, the flag Page 8, Reg 1, D(1) toggles.
The flag in Page 8, Register 1, D(1) indicates which of the two buffers is actually in use.
54
APPLICATION INFORMATION
Copyright 2009–2010, Texas Instruments Incorporated
Product Folder Link(s): TLV320AIC36
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| TLV320AIC36IZQER | 功能描述:接口—CODEC Low Pwr Stereo Aud Codec RoHS:否 制造商:Texas Instruments 類型: 分辨率: 轉(zhuǎn)換速率:48 kSPs 接口類型:I2C ADC 數(shù)量:2 DAC 數(shù)量:4 工作電源電壓:1.8 V, 2.1 V, 2.3 V to 5.5 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:DSBGA-81 封裝:Reel |
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