參數(shù)資料
型號： TLV320AIC36IZQE
廠商： TEXAS INSTRUMENTS INC
元件分類： 消費家電
英文描述： SPECIALTY CONSUMER CIRCUIT, PBGA80
封裝： 5 X 5 MM, GREEN, PLASTIC, VFBGA-80
文件頁數(shù)： 113/165頁
文件大小： 1895K
代理商： TLV320AIC36IZQE
www.ti.com
SBAS387A – MAY 2009 – REVISED JUNE 2010
The high power output drivers can also be programmed to power up first with the output level control in a
highly attenuated state, and then the output driver will automatically slowly reduce the output attenuation
to reach the desired output level setting programmed.
The signal routing for the high power drivers is configured using Page 2, Registers 45 through 72.
5.12.3 Short-Circuit Output Protection
The TLV320AIC36 includes programmable short-circuit protection for the high power output drivers, for
maximum flexibility in a given application. By default, if these output drivers are shorted, they will
automatically limit the maximum amount of current that can be sourced to or sunk from a load, thereby
protecting the device from an over-current condition. In this mode, the user can read Page-0/Reg-95 to
determine whether the part is in short-circuit protection or not, and then decide whether to program the
device to power down the output drivers. However, the device includes further capability to automatically
power down an output driver whenever it does into short-circuit protection, without requiring intervention
from the user. In this case, the output driver will stay in a power down condition until the user specifically
programs it to power down and then power back up again, to clear the short-circuit flag.
5.13 DAC Gain Setting
5.13.1 Digital Volume Control
The TLV320AIC36 signal processing blocks incorporate a digital volume control block that can control the
volume of the playback signal from +24 dB to –63.5 dB in steps of 0.5 dB. These can be controlled by
writing to Page 0, Register 65 and 66. The volume control of left and right channels by default can be
controlled independently, however by programming Page 0, Reg 64, D(1:0), they can be made
interdependent. The volume changes are soft-stepped in steps of 0.5 dB to avoid audible artifacts during
gain change. The rate of soft-stepping can be controlled by programming Page 0, Reg 63, D(1:0) to either
one step per frame (DAC_FS) or one step per 2 frames. The soft-stepping feature can also be entirely
disabled. During soft-stepping the value of the actual applied gain would differ from the programmed gain
in register. The TLV320AIC36 gives a feedback to the user in form of register readable flag to indicate that
soft-stepping is currently in progress. The flags for left and right channels can be read back by reading
Page 0, Reg 37, D(2) and D(1) respectively. A value of 0 in these flags indicates a soft-stepping operation
in progress, and a value of 1 indicates that soft-stepping has completed. A soft-stepping operation comes
into effect during a) power-up, when the volume control soft-steps from –63.5 dB to programmed gain
value b) volume change by user when DAC is powered up and c) power-down, when the volume control
block soft-steps to –63.5 dB before powering down the channel.
5.13.2 Dynamic Range Compression
Typical music signals are characterized by crest factors, the ratio of peak signal power to average signal
power, of 12 dB or more. In order to avoid audible distortions due to clipping of peak signals, the gain of
the DAC channel must be adjusted so as not to cause hard clipping of peak signals. As a result, during
nominal periods, the applied gain is low, causing the perception that the signal is not loud enough. To
overcome this problem, the DRC in the TLV320AIC36 continuously monitors the output of the DAC Digital
Volume control to detect its power level with respect to 0 dB FS. When the power level is low, it increases
the input signal gain to make it sound louder. At the same time, if a peaking signal is detected, it
autonomously reduces the applied gain to avoid hard clipping. This results in sounds more pleasing to the
ear as well as sounding louder during nominal periods.
The DRC functionality in the TLV320AIC36 is implemented by a combination of Processing Blocks in the
DAC channel as described in Section 5.11.2.
The DRC can be disabled by writing into Page 0, Reg 68, D(6:5).
Copyright 2009–2010, Texas Instruments Incorporated
APPLICATION INFORMATION
51
Product Folder Link(s): TLV320AIC36
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