參數(shù)資料
型號： TLV320AIC36IZQE
廠商： TEXAS INSTRUMENTS INC
元件分類： 消費(fèi)家電
英文描述： SPECIALTY CONSUMER CIRCUIT, PBGA80
封裝： 5 X 5 MM, GREEN, PLASTIC, VFBGA-80
文件頁數(shù)： 98/165頁
文件大?。?/td> 1895K
代理商： TLV320AIC36IZQE
DS
LEFT ADC
CICFILTER
RIGHT ADC
CICFILTER
miniDSP
Engine
ADC_MOD_CLK
G
P
IO
1
G
P
IO
2
D
IG
M
IC
_
C
L
K
D
S
D
_
C
L
K
D
S
D
_
D
A
T
A
DIG_MIC_IN
G
P
IO
1
D
IG
M
IC
_
D
A
T
A
D
IN
SelectedwithPage0
Registers 120 - 125
SelectedwithPage0
Register 81
DS
LEFT
RIGHT
LEFT
RIGHT
LEFT
RIGHT
ADC_MOD_CLK
DIG_MIC_IN
SBAS387A – MAY 2009 – REVISED JUNE 2010
www.ti.com
5.9
ADC Special Functions
5.9.1
Digital Microphone Function
In addition to supporting analog microphones, the TLV320AIC36 also supports interfacing to a digital
microphone. The internal ADC_MOD_CLK is available on pins selected with Page 0 Registers 120 – 125
as a digital microphone clock. The single-bit output of the external digital microphone can be connected to
the GPIO1, DIGMIC_DATA, or the DIN pins as selected with Page 0 Register 81 as shown in Figure 5-16
Figure 5-16. Digital Microphone in TLV320AIC36
Internally, the TLV320AIC36 samples the digital microphone left channel data using the rising edge of the
microphone clock and the right channel data using the falling edge of the clock as shown in Figure 5-17.
Figure 5-17. Timing Diagram for Digital Microphone Interface
The digital-microphone mode can be selectively enabled for only-left, only-right, or stereo channels. When
the digital microphone mode is enabled, the analog section of the ADC can be powered down and
bypassed for power efficiency. The AOSR value for the ADC channel must be configured to select the
desired decimation ratio to be achieved based on the external digital microphone properties.
5.9.2
Channel-to-Channel Phase Adjustment
The TLV320AIC36 has a built-in feature to fine-adjust the phase between the stereo ADC record signals.
The phase compensation is particularly helpful to adjust delays when using dual microphones for noise
cancellation.
This delay can be controlled in fine amounts in the following fashion.
Delay(7:0) = Page 0/Register 85/D(7:0)
Where:
38
APPLICATION INFORMATION
Copyright 2009–2010, Texas Instruments Incorporated
Product Folder Link(s): TLV320AIC36
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