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| 型號： | TLV320AIC36IZQE |
| 廠商： | TEXAS INSTRUMENTS INC |
| 元件分類： | 消費家電 |
| 英文描述： | SPECIALTY CONSUMER CIRCUIT, PBGA80 |
| 封裝： | 5 X 5 MM, GREEN, PLASTIC, VFBGA-80 |
| 文件頁數(shù)： | 115/165頁 |
| 文件大?。?/td> | 1895K |
| 代理商： | TLV320AIC36IZQE |
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www.ti.com
SBAS387A – MAY 2009 – REVISED JUNE 2010
become disabled. For example, if the DRC Threshold is set to –12 dBFS and DRC Hysteresis is set to 3
dB, then if the gain compressions in the DRC is inactive, the output of the DAC Digital Volume Control
must exceed –9 dBFS before gain compression due to the DRC is activated. Similarly, when the gain
compression in the DRC is active, the output of the DAC Digital Volume Control needs to fall below -15
dBFS for gain compression in the DRC to be deactivated. The DRC Hysteresis feature prevents the rapid
activation and de-activation of gain compression in the DRC in cases when the output of DAC Digital
Volume Control rapidly fluctuates in a narrow region around the programmed DRC Threshold. By
programming the DRC Hysteresis as 0 dB, the hysteresis action is disabled.
The recommended value of DRC hysteresis is 3 dB.
5.13.2.3 DRC Hold
The DRC Hold is intended to slow the start of decay for a specified period of time in response to a
decrease in energy level. To minimize audible artifacts, it is recommended to set the DRC Hold time to 0
through programming Page 0, Register 69, D(6:3) = 0000.
5.13.2.4 DRC Attack Rate
When the output of the DAC Digital Volume Control exceeds the programmed DRC Threshold, the gain
applied in the DAC Digital Volume Control is progressively reduced to avoid the signal from saturating the
channel. This process of reducing the applied gain is called Attack. To avoid audible artifacts, the gain is
reduced slowly with a rate equaling the Attack Rate programmable using Page 0, Register 70, D(7:4).
Attack Rates can be programmed from 4 dB gain change per 1/DAC_FS to 1.2207e-5 dB gain change per
1/DAC_FS.
Attack Rates should be programmed such that before the output of the DAC Digital Volume control can
clip, the input signal should be sufficiently attenuated. High Attack Rates can cause audible artifacts, and
too-slow Attack Rates may not be able to prevent the input signal from clipping.
The recommended value of DRC attack rate is 1.9531e-4 dB per 1/DAC_FS.
5.13.2.5 DRC Decay Rate
When the DRC detects a reduction in output signal swing beyond the programmed DRC Threshold, the
DRC enters a Decay state, where the applied gain in Digital Volume Control is gradually increased to
programmed values. To avoid audible artifacts, the gain is slowly increased with a rate equal to the Decay
Rate programmed through Page 0, Register 70, D(3:0). The Decay Rates can be programmed from
1.5625e-3 dB per 1/DAC_FS to 4.7683e-7 dB per 1/DAC_FS. If the Decay Rates are programmed too
high, then sudden gain changes can cause audible artifacts. However, if it is programmed too slow, then
the output may be perceived as too low for a long time after the peak signal has passed.
The recommended Value of DRC Attack Rate is 2.4414e-5 dB per 1/DAC_FS.
5.13.2.6 Example Setup for DRC
PGA Gain = 12 dB
Threshold = –24 dB
Hysteresis = 3 dB
Hold time = 0 ms
Attack Rate = 1.9531e-4 dB per 1/DAC_FS
Decay Rate = 2.4414e-5 dB per 1/DAC_FS
Script
#Go to Page 0 w 30 00 00 #DAC => 12 db gain left w 30 41 18 #DAC => 12 db gain right w 30 42 18
#DAC => DRC Enabled for both channels, Threshold = -24 db, Hysteresis = 3 dB w 30 44 7F #DRC
Hold = 0 ms, Rate of Changes of Gain = 0.5 dB/Fs' w 30 45 00 #Attack Rate = 1.9531e-4 dB/Frame
, DRC Decay Rate =2.4414e-5 dB/Frame w 30 46 B6 #Go to Page 9 w 30 00 09 #DRC HPF w 30 0E 7F AB
00 80 7F 56 #DRC LPF W 30 14 00 11 00 11 7F DE
Copyright 2009–2010, Texas Instruments Incorporated
APPLICATION INFORMATION
53
Product Folder Link(s): TLV320AIC36
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