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參數(shù)資料
| 型號： | TLV320AIC36IZQE |
| 廠商： | TEXAS INSTRUMENTS INC |
| 元件分類： | 消費家電 |
| 英文描述： | SPECIALTY CONSUMER CIRCUIT, PBGA80 |
| 封裝： | 5 X 5 MM, GREEN, PLASTIC, VFBGA-80 |
| 文件頁數(shù)： | 80/165頁 |
| 文件大?。?/td> | 1895K |
| 代理商： | TLV320AIC36IZQE |
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www.ti.com
SBAS387A – MAY 2009 – REVISED JUNE 2010
5.2.2
Analog Pins
Analog functions can also be configured to a large degree. For minimum power consumption, analog
blocks are powered down by default. The blocks can be powered up with fine granularity according to the
application needs.
The possible analog routings of analog input pins to ADCs and output amplifiers as well as the routing
from DACs to output amplifiers can be seen in Figure 5-2.
5.2.3
Power Supply
The TLV320AIC36 power management unit generates all of the analog supply voltages from a single
nominal 2.5 V supply. The power management unit consists of two positive LDOs, one which generates a
nominal +1.75 V supply for the input PGA and ADC section and another which generates a nominal +1.65
V for the DAC and audio amplifier section. A negative charge pump generates an unregulated negative
voltage from the unregulated positive supply; a negative LDO generates a nominal –1.65 V supply for the
DAC and audio amplifier section from this unregulated negative voltage. See Figure 5-48 for details on
typical power supply connections.
5.2.4
Clocking
To minimize power consumption, the system ideally provides a master clock that is a suitable integer
multiple of the desired sampling frequencies. In such cases, internal dividers can be programmed to set
up the required internal clock signals at very low power consumption. For cases where such master clocks
are not available, the built-in PLL can be used to generate a clock signal that serves as an internal master
clock. In fact, this master clock can also be routed to an output pin and can be used elsewhere in the
system. The clock system is flexible enough that it allows the internal clocks to be derived directly from an
external clock source, while the PLL generates an other clock that is used only outside the TLV320AIC36.
5.3
miniDSP
The TLV320AIC36 features two miniDSP cores. The first miniDSP core is tightly coupled to the ADC, the
second miniDSP core is tightly coupled to the DAC. The fully programmable algorithms for the miniDSP
must be loaded into the device after power up. The miniDSPs have direct access to the digital stereo
audio stream on the ADC and on the DAC side, offering the possibility for advanced, very low group delay
DSP algorithms.
5.3.1
Software
Software development for the TLV320AIC36 is supported through TI's comprehensive PurePath Studio
Development Environment. A powerful, easy-to-use tool designed specifically to simplify software
development on the TI miniDSP audio platform. The Graphical Development Environment consists of a
library of common audio functions that can be dragged-and-dropped into an audio signal flow and
graphically connected together. The DSP code can then be assembled from the graphical signal flow with
the click of a mouse.
Visit the TLV320AIC36 product folder on www.ti.com to learn more about PurePath Studio and the latest
status on available, ready-to-use DSP algorithms.
Copyright 2009–2010, Texas Instruments Incorporated
APPLICATION INFORMATION
21
Product Folder Link(s): TLV320AIC36
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| TLV320AIC36IZQER | 功能描述:接口—CODEC Low Pwr Stereo Aud Codec RoHS:否 制造商:Texas Instruments 類型: 分辨率: 轉(zhuǎn)換速率:48 kSPs 接口類型:I2C ADC 數(shù)量:2 DAC 數(shù)量:4 工作電源電壓:1.8 V, 2.1 V, 2.3 V to 5.5 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:DSBGA-81 封裝:Reel |
| TLV320ALC23 | 制造商:TI 制造商全稱:Texas Instruments 功能描述:Evaluation Platform for the TLV320ALC23 Stereo Audio CODEC and TLV230DAC23 Stereo DAC |
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| TLV320DA26IRHBG4 | 功能描述:音頻數(shù)/模轉(zhuǎn)換器 IC Lo-Pwr Ster DAC w/Hdphn/Spkr Amp RoHS:否 制造商:Texas Instruments 轉(zhuǎn)換器數(shù)量: 分辨率:16 bit 接口類型:I2S, UBS 轉(zhuǎn)換速率: 信噪比:98 dB 工作電源電壓:5 V DAC 輸出端數(shù)量:2 工作溫度范圍:- 25 C to + 85 C 電源電流:23 mA 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:TQFP-32 封裝:Reel |
| TLV320DAC23 | 制造商:TI 制造商全稱:Texas Instruments 功能描述:STEREO AUDIO D/A CONVERTER, 8-TO 96KHZ WITH INTERGRATED HEADPHONE AMPLIFIER |
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