參數(shù)資料
型號： TLV320AIC36IZQE
廠商： TEXAS INSTRUMENTS INC
元件分類： 消費家電
英文描述： SPECIALTY CONSUMER CIRCUIT, PBGA80
封裝： 5 X 5 MM, GREEN, PLASTIC, VFBGA-80
文件頁數(shù)： 8/165頁
文件大?。?/td> 1895K
代理商： TLV320AIC36IZQE
www.ti.com
SBAS387A – MAY 2009 – REVISED JUNE 2010
6.2.80 Page 0 / Register 83:
Left ADC Channel Volume Control Register
READ/
RESET
BIT
DESCRIPTION
WRITE
VALUE
D7
R
0
Reserved. Write only default values
D6–D0
R/W
000 0000
Left ADC Channel Volume Control
100 0000-110 1000: Reserved. Do not use
110 0111: Left ADC Channel Volume = -12 dB
110 0110: Left ADC Channel Volume = -11.5 dB
110 0101: Left ADC Channel Volume = -11.0 dB
…
111 1111: Left ADC Channel Volume = -0.5 dB
000 0000: Left ADC Channel Volume = 0.0 dB
000 0001: Left ADC Channel Volume = 0.5 dB
...
010 0110: Left ADC Channel Volume = 19.0 dB
010 0111: Left ADC Channel Volume = 19.5 dB
010 1000: Left ADC Channel Volume = 20.0 dB
010 1001-011 1111: Reserved. Do not use
6.2.81 Page 0 / Register 84:
Right ADC Channel Volume Control Register
READ/
RESET
BIT
DESCRIPTION
WRITE
VALUE
D7
R
0
Reserved. Write only default values
D6–D0
R/W
000 0000
Right ADC Channel Volume Control
100 0000-110 1000: Reserved. Do not use
110 0111: Right ADC Channel Volume = -12 dB
110 0110: Right ADC Channel Volume = -11.5 dB
110 0101: Right ADC Channel Volume = -11.0 dB
…
111 1111: Right ADC Channel Volume = -0.5 dB
000 0000: Right ADC Channel Volume = 0.0 dB
000 0001: Right ADC Channel Volume = 0.5 dB
...
010 0110: Right ADC Channel Volume = 19.0 dB
010 0111: Right ADC Channel Volume = 19.5 dB
010 1000: Right ADC Channel Volume = 20.0 dB
010 1001-011 1111: Reserved. Do not use
6.2.82 Page 0 / Register 85:
ADC Phase Adjust Register
READ/
RESET
BIT
DESCRIPTION
WRITE
VALUE
D7–D0
R/W
0000 0000
ADC Phase Compensation Control
1000 0000-1111 1111: Left ADC Channel Data is delayed with respect to Right ADC Channel
Data. For details of delayed amount please see the description of Phase Compensation in the
Overview section.
0000 0000: Left and Right ADC Channel data are not delayed with respect to each other
0000 0001-0111 1111: Right ADC Channel Data is delayed with respect to Left ADC Channel
Data. For details of delayed amount please see the description of Phase Compensation in the
Overview section.
Copyright 2009–2010, Texas Instruments Incorporated
REGISTER MAP
105
Product Folder Link(s): TLV320AIC36
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