參數(shù)資料
型號: TLV320AIC36IZQE
廠商: TEXAS INSTRUMENTS INC
元件分類: 消費家電
英文描述: SPECIALTY CONSUMER CIRCUIT, PBGA80
封裝: 5 X 5 MM, GREEN, PLASTIC, VFBGA-80
文件頁數(shù): 127/165頁
文件大?。?/td> 1895K
代理商: TLV320AIC36IZQE
LD(n)
LD(n+1)
WORD
CLOCK
BIT
CLOCK
DATA
-
1
-
2
-
3
2
1
0
3
-
1
-
2
-
3
2
1
0
3
-
1
-
2
N N N
-
3
RD(n)
LEFT CHANNEL
RIGHT CHANNEL
LD(n)=n'thsampleofleftchanneldata
RD(n)=n'thsampleofrightchanneldata
LD(n)
LD(n+1)
WORD
CLOCK
BIT
CLOCK
DATA
-
1
-
2
-
3
2
1
0
3
-
1
-
2
-
3
2
1
0
3
-
1
-
2
N N N
-
3
RD(n)
LEFT CHANNEL
RIGHT CHANNEL
LD(n)=n'thsampleofleftchanneldata
RD(n)=n'thsampleofrightchanneldata
LD(n)
LD(n+1)
WORD
CLOCK
BIT
CLOCK
DATA
3
N
-
1
N
-
2
N
-
3
2
1
0
3
N
-
1
N
-
2
N
-
3
2
1
0
3
N
-
1
N
-
2
N
-
3
RD(n)
LEFT CHANNEL
RIGHT CHANNEL
LD(n)=n'thsampleofleftchanneldata
RD(n)=n'thsampleofrightchanneldata
SBAS387A – MAY 2009 – REVISED JUNE 2010
www.ti.com
Figure 5-36. Timing Diagram for Left-Justified Mode
Figure 5-37. Timing Diagram for Left-Justified Mode with Offset=1
Figure 5-38. Timing Diagram for Left-Justified Mode with Offset = 0 and Inverted Bit Clock
For Left-Justified mode, the number of bit-clocks per frame should be greater than twice the programmed
word-length of the data. Also, the programmed offset value should be less than the number of bit-clocks
per frame by at least the programmed word-length of the data.
5.17.1.3 I2S Mode
The Audio Interface of the TLV320AIC36 can be put into Right Justified Mode by programming Page 0,
Register 25, D(7:6) = to 00. In I2S mode, the MSB of the left channel is valid on the second rising edge of
the bit clock after the falling edge of the word clock. Similarly the MSB of the right channel is valid on the
second rising edge of the bit clock after the rising edge of the word clock.
64
APPLICATION INFORMATION
Copyright 2009–2010, Texas Instruments Incorporated
Product Folder Link(s): TLV320AIC36
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