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| 型號： | TLV320AIC36IZQE |
| 廠商： | TEXAS INSTRUMENTS INC |
| 元件分類： | 消費(fèi)家電 |
| 英文描述： | SPECIALTY CONSUMER CIRCUIT, PBGA80 |
| 封裝： | 5 X 5 MM, GREEN, PLASTIC, VFBGA-80 |
| 文件頁數(shù)： | 138/165頁 |
| 文件大?。?/td> | 1895K |
| 代理商： | TLV320AIC36IZQE |
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LF
OSC
DETECT
DIVIDER1
DETECT
DIVIDER2
Page2,Reg112
Page2,Reg20
Page2,Reg21
Page2,Reg20
Page2,Reg21
OpenCircuit
Detection
HPL PIN
HPRPIN
RECL PIN
RECRPIN
HOOKPIN
HPL STATUS
HPRSTATUS
RECL STATUS
RECRSTATUS
HOOKSTATUS
HPL INTERRUPT
HPRINTERRUPT
RECL INTERRUPT
RECRINTERRUPT
HOOKINTERRUPT
Page0,Reg50
Page0,Reg51
SBAS387A – MAY 2009 – REVISED JUNE 2010
www.ti.com
5.19.2 Low-Impedance Detection
The TLV320AIC36 supports detection of low impedance (<50 ohm) to ground on the HPL, HPR, RECL,
RECR, and HOOK pins. Detection can either be performed manually using an I2C register access or
periodically sampled to generate an interrupt.
Manual detection is performed by enabling manual detection using Page 2, Register 108 and reading back
the status register on Page 2, Register 109 on a per-pin basis. For power reasons, it is recommended that
the enables for the manual detection in Register 108 are cleared after the status values are read from
Register 108.
The periodic sampling rate uses the same LF oscillator and detect dividers as the headset detection see
Figure 5-52. Periodic OC Detection Sampling
5.19.3 General-Purpose I/O
The TLV320AIC36 provides flexible I/O multiplexing to support digital microphone input, class-D amplifier
output, interrupt output, and general purpose digital I/O options. Page 0 Registers 120 through 125 are
used
to
control
the
GPIO1,
GPIO2,
GPIO4/DIGMIC_CLK,
GPIO3/DIGMIC_DATA,
GPIO6/BITSTREAM_CLK, and GPIO5/BITSTREAM_DATA pin functions.
5.19.4 Interrupts
The TLV320AIC36 can generate host interrupts originating from miniDSP, power threshold, LDO over
current, detect, and hook sources. Each source can be individually enabled and associated with two
separate interrupt groups (INT1 and INT2) and routed to device pins. Each pin provides active high, active
low or open drain output capabilities.
The status of each interrupt source is available in a “sticky bit” and a real-time format. A sticky bit is a
status bit that is set by the interrupting source and remains set until cleared using an I2C register write.
Real-time status bits provide a live read-back of the interrupting condition. Some interrupts can be
programmed to assert based on rising, falling, or changes of state for additional user customization.
To associate an interrupt source with an interrupt group, the corresponding interrupt enable register bit
must be set. Multiple interrupt sources may be used for one interrupt group. If multiple enabled interrupts
are asserted in an interrupt group, all sticky bits must be cleared before the device pin is de-asserted. All
interrupts listed in Table 5-22can be selectively assigned to the INT1 or INT2 group.
Table 5-22. Interrupt Sources
Interrupt Source
Type
Right DAC Signal Power is above Signal Threshold of DRC
DAC engine
Left DAC Signal Power is above Signal Threshold of DRC
DAC engine
ADC Barrel Shifter Output Overflow Flag
ADC engine
Right ADC Overflow Flag
ADC engine
74
APPLICATION INFORMATION
Copyright 2009–2010, Texas Instruments Incorporated
Product Folder Link(s): TLV320AIC36
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