
(P2R48)
(P2R46)
(P2R49)
(P2R45)
(P2R50)
(P2R47)
HPRVolume
(0 to -78dB)
(P2R62)
(P2R60)
(P2R63)
(P2R59)
(P2R64)
(P2R61)
DAC_L
DAC_R
LINEIN_L
LINEIN_R
PGA_L
PGA_R
RECL Volume
(0 to -78dB)
(P2R55)
(P2R53)
(P2R56)
(P2R52)
(P2R57)
(P2R54)
HPL Volume
(0 to -78dB)
(P2R69)
(P2R67)
(P2R70)
(P2R66)
(P2R71)
(P2R68)
RECRVolume
(0 to -78dB)
(P2R86)
LINEOUT_L Volume
(0 to -78dB)
Gain:
0 to +9 dB
(P2R90)
(P2R88)
(P2R91)
(P2R87)
(P2R92)
(P2R89)
(P2R93)
LINEOUT_RVolume
(0 to -78dB)
(P2R83)
(P2R81)
(P2R84)
(P2R80)
(P2R85)
(P2R82)
Gain:
0 to +9 dB
(P2R65)
+
DAC_L
DAC_R
LINEIN_L
LINEIN_R
PGA_L
PGA_R
Gain:
0 to +9 dB
(P2R58)
+
DAC_L
DAC_R
LINEIN_L
LINEIN_R
PGA_L
PGA_R
Gain:
0 to +9 dB
(P2R51)
+
DAC_L
DAC_R
LINEIN_L
LINEIN_R
PGA_L
PGA_R
Gain:
0 to +9 dB
(P2R72)
+
(P2R36)
DAC_L
DAC_R
LINEIN_L
LINEIN_R
PGA_L
PGA_R
DAC_L
DAC_R
LINEIN_L
LINEIN_R
PGA_L
PGA_R
+
Gain:
0 to +9 dB
(P1R59)
Gain:
0 to +46.5 dB
LINEIN_L
InputMUX
(P1R52)
MIC1_P
EXTMIC_P
MIC1_M
InputMUX
(P1R54)
EXTMIC_M
VCM_ADC
(P1R60)
Gain:
0 to +46.5 dB
VCM_ADC
InputMUX
(P1R57)
EXTMIC_M
MIC2_M
EXTMIC_P
InputMUX
(P1R55)
MIC2_P
LINEIN_R
V
C
M
(P
1
R
1
0
)
ADC
L
+
ADC
R
DAC
L
DAC
R
(P2R40)
LINEIN _R (G 7)
MIC 2_P (H8)
MIC2 _M (G 8)
EXTMIC _M (J7)
VCM_ ADC (J9)
MIC1_M (H6)
EXTMIC _P (H7)
MIC1_P (J6)
LINEIN _L (G 6)
LINEOUT _RM (A8 )
LINEOUT _RP (C6 )
LINEOUT _LM (A7)
LINEOUT _LP (B6 )
HPL (F7)
HPR (F9)
HP_ COM (J8)
GND _HP (E7)
RECL (D8)
RECR ( D9)
DACPwr (P2R37 )
DACCurrentCtrl
(P2R107 )
ADCPwr (P0 R81 )
OpenCircuit
Detect
(P2R108)
OpenCircuit
Detect
(P2R108)
OpenCircuit
Detect
(P2R108)
OpenCircuit
Detect
(P2R108)
AlloutputVolume
Gainsarein 0. 5dBsteps
AlloutputGains
arepositivein 1dBsteps
CommonControls:
SCProtection:(P2R38)
GainSoft-Stepping:(P2R40)
PopReduction:(P2R42)
miniDSP
SBAS387A – MAY 2009 – REVISED JUNE 2010
www.ti.com
5.4
Analog Routing
Figure 5-2. Analog Routing Diagram
5.4.1
Analog Bypass
The TLV320AIC36 offers two analog-bypass modes, line input bypass and PGA bypass mode. For these
modes, all LDOs and the ADC must be enabled. The DAC does not need to be enabled to save power.
5.4.2
Line Input Bypass
This mode routes LINEINL/R to any of the output amplifiers by configuring Page 2, Register 40 and by
programming the output amplifiers to select one or both line inputs. See Figure 5-2. Under normal bypass
operation, the line inputs are AC-coupled to the LINEIN_L/LINEIN_R pins. The ADC generates an internal
commode mode voltage for these signals before the bypass amplifiers. The bypass amplifiers have a fixed
gain of 0 dB for single-ended output to HPL_R and RECL_R, and 6-dB gain for differential output to
LINEOUT_L/LINEOUT_R.
To save power, the ADC can be disabled and an external common mode voltage can be generated for
these pins. A simple 20k
/20k resistor divider from AVDD_ADC to GND_ADC is sufficient with some
compromise in performance.
5.4.3
PGA Bypass
In this mode, the mic or line input signals are amplified by the PGA and routed to the output amplifiers.
See figure 5-2. This mode is enabled by selecting the input mux, setting the PGA gain, and programming
the output amplifiers to select one or both PGA outputs.
22
APPLICATION INFORMATION
Copyright 2009–2010, Texas Instruments Incorporated