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參數(shù)資料
| 型號(hào)： | TLV320AIC36IZQE |
| 廠商： | TEXAS INSTRUMENTS INC |
| 元件分類： | 消費(fèi)家電 |
| 英文描述： | SPECIALTY CONSUMER CIRCUIT, PBGA80 |
| 封裝： | 5 X 5 MM, GREEN, PLASTIC, VFBGA-80 |
| 文件頁(yè)數(shù)： | 134/165頁(yè) |
| 文件大?。?/td> | 1895K |
| 代理商： | TLV320AIC36IZQE |
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SBAS387A – MAY 2009 – REVISED JUNE 2010
www.ti.com
The charge pump is enabled by setting Page 2, Register 71, D0=1. By default the charge pump uses a
divided version of BCLK as its clock, but setting Page 2, Register 71, D1=1 will cause it to use MCLK
instead. The frequency division is controlled by two registers: Page 2, Register 72 contains the number of
clock cycles that the charge pump clock is high (minus one), while Page 2, Register 73 contains the
number of clock cycles the charge pump is low (minus one). As an example, if the default values of 11 are
used in these two registers the charge pump clock frequency is BCLK/24.
The charge pump frequency should be programmed between 400 and 500 kHz. If no very high current
loads are being driven from the amplifier section, this frequency can be reduced to save power. Care
should be taken to keep the charge pump frequency above the audio range.
5.18.2 LDOs
The unregulated input for the two positive LDOs is AVDD_REG. AVDD1 is the output of the high-power
regulator meant to drive the DAC and output amplifiers; a minimum of 10mF (maximum 100mF)
capacitance is required on this pin for LDO stability. The capacitance can be split between AVDD1,
AVDD_DAC, and AVDD_HP as long as the trace resistance plus the capacitor ESR is less than 400m
Ω.
Similarly a minimum of 1mF (maximum 10mF) is required on AVDD2, the output of the low-power regulator
intended to supply the preamp and ADC section.
The input to the negative regulator is connected internally to the charge pump output. AVSS1 is the output
of the high-power regulator meant to drive the DAC and output amplifiers; a minimum of 10mF (maximum
100mF) capacitance is required on this pin for LDO stability. The capacitance can be split between AVSS1,
AVSS_DAC, and AVSS_HP as long as the trace resistance plus the capacitor ESR is less than 400m
Ω.
The regulators are enabled by the lower 3 bits of Page 2, Register 74. The negative regulator should be
enabled only after the charge pump is enabled, otherwise the charge pump may not start up properly.
By default, the regulators start up in a current-limited mode to prevent high inrush currents. The two
high-power regulators (AVDD1 and AVSS1) are limited to 50 mA, while the low-power regulator (AVDD2)
is limited to 5 mA. After the regulators have had time to power up, remove the current limit by clearing the
least-significant 3 bits of Page 2, Register 76.
Short circuit protection for the regulators may be disabled through Page 2, Register 77. The nominal
output level of the regulators can be programmed through Page 2, Register 78.
5.18.3 Low Power Mode
In addition to the standard configuration, the PMU can be used in two alternative configurations to further
reduce power consumption. These low power modes sacrifice some performance for power savings. See
sections 3.7 and 3.8 for typical performance electrical characteristics.
The first low power (LP) mode is capable of reducing power dissipation to 14mW for DAC to headphone
playback. Max headphone output power is 20mW per channel. Referring to Figure 5-48, the changes are:
1. AVDD_REG supply should be reduced to 1.8V (1.65V min)
2. This 1.8V supply also drives AVDD_ADC. AVDD2 is not connected to AVDD_ADC, and the AVDD
LDO is disabled.
3. Register settings (see Section 5.21): DAC VDD LDO=1.5V, DAC VSS LDO=1.5V, ADC VDD LDO =
off, Bias current = low power setting, DACSP = PRB_P17, REC,LO,HP gain=-2dB.
The second ultra low power (ULP) mode is capable of reducing power dissipation to 10mW for DAC to
headphone playback. Max output power is 10mW. Maximum input voltage for the ADC is reduced by 6dB.
Referring to Figure 5-48, the changes are
1. AVDD_REG supply should be reduced to 1.5V (1.4V min)
2. The 1.5V supply also drives AVDD_ADC, AVDD_DAC, AVDD_HP, DVDD.
3. AVSS_REG is directly connected to AVSS_DAC and AVSS_HP.
4. DAC VDD LDO, DAC VSS LDO, ADC VDD LDO are not used, powered down and disconnected.
70
APPLICATION INFORMATION
Copyright 2009–2010, Texas Instruments Incorporated
Product Folder Link(s): TLV320AIC36
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| TLV320AIC36IZQER | 功能描述:接口—CODEC Low Pwr Stereo Aud Codec RoHS:否 制造商:Texas Instruments 類型: 分辨率: 轉(zhuǎn)換速率:48 kSPs 接口類型:I2C ADC 數(shù)量:2 DAC 數(shù)量:4 工作電源電壓:1.8 V, 2.1 V, 2.3 V to 5.5 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:DSBGA-81 封裝:Reel |
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| TLV320DAC23 | 制造商:TI 制造商全稱:Texas Instruments 功能描述:STEREO AUDIO D/A CONVERTER, 8-TO 96KHZ WITH INTERGRATED HEADPHONE AMPLIFIER |
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