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| 型號： | TLV320AIC36IZQE |
| 廠商： | TEXAS INSTRUMENTS INC |
| 元件分類： | 消費(fèi)家電 |
| 英文描述： | SPECIALTY CONSUMER CIRCUIT, PBGA80 |
| 封裝： | 5 X 5 MM, GREEN, PLASTIC, VFBGA-80 |
| 文件頁數(shù)： | 114/165頁 |
| 文件大小： | 1895K |
| 代理商： | TLV320AIC36IZQE |
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1
15
1
0
HPF
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2
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H
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1
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LPF
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SBAS387A – MAY 2009 – REVISED JUNE 2010
www.ti.com
The DRC typically works on the filtered version of the input signal. The input signals have no audio
information at DC and extremely low frequencies; however they can significantly influence the energy
estimation function in DRC. Also most of the information about signal energy is concentrated in the low
frequency region of the input signal.
To estimate the energy of the input signal, the signal is first fed the DRC high-pass filter, and then fed to
the DRC low-pass filter. These filters are implemented as first-order IIR filters given by
(11)
(12)
The coefficients for these filters are 16 bits wide in twos complement and are user programmable through
register write as given in Table 5-18
Table 5-18. DRC HPF and LPF Coefficients
Coefficient
Location
HPF N0
C71 Page 9, Register 14 and 15
HPF N1
C72 Page 9, Register 16 and 17
HPF D1
C73 Page 9, Register 18 and 19
LPF N0
C74 Page 9, Register 20 and 21
LPF N1
C75 Page 9, Register 22 and 23
LPF D1
C76 Page 9, Register 24 and 25
The default values of these coefficients implement a high-pass filter with a cut-off at 0.00166*DAC_FS,
and a low-pass filter with a cutoff at 0.00033 * DAC_FS.
The output of the DRC high-pass filter is fed to the Processing Block selected for the DAC Channel. The
absolute value of the DRC-LPF filter is used for energy estimation within the DRC.
The gain in the DAC Digital Volume Control is controlled by Page 0, Register 65 and 66. When the DRC is
enabled, the applied gain is a function of the Digital Volume Control register setting and the output of the
DRC.
The DRC parameters are described in sections that follow.
5.13.2.1 DRC Threshold
The DRC Threshold represents the level of the DAC playback signal at which the gain compression
becomes active. The output of the digital volume control in the DAC is compared with the set threshold.
The threshold value is programmable by writing to register Page 0, Register 68, D(4:2). The Threshold
value can be adjusted between –3 dBFS to –24 dBFS in steps of 3 dB. Keeping the DRC Threshold value
too high may not leave enough time for the DRC block to detect peaking signals, and can cause
excessive distortion at the outputs. Keeping the DRC Threshold value too low can limit the perceived
loudness of the output signal.
The recommended DRC-Threshold value is –24 dB.
When the output signal exceeds the set DRC Threshold, the interrupt flag bits at Page 0, Register 44,
D(3:2) are updated. These flag bits are 'sticky' in nature, and are reset only after they are read back by the
user. The nonsticky versions of the interrupt flags are also available at Page 0, Register 46, D(3:2).
5.13.2.2 DRC Hysteresis
DRC Hysteresis is programmable by writing to Page 0, Register 68, D(1:0). It can be programmed to
values between 0 dB and 3 dB in steps of 1 dB. It is a programmable window around the programmed
DRC Threshold that must be exceeded for a disabled DRC to become enabled, or an enabled DRC to
52
APPLICATION INFORMATION
Copyright 2009–2010, Texas Instruments Incorporated
Product Folder Link(s): TLV320AIC36
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