參數(shù)資料
型號： TLV320AIC36IZQE
廠商： TEXAS INSTRUMENTS INC
元件分類： 消費家電
英文描述： SPECIALTY CONSUMER CIRCUIT, PBGA80
封裝： 5 X 5 MM, GREEN, PLASTIC, VFBGA-80
文件頁數(shù)： 143/165頁
文件大?。?/td> 1895K
代理商： TLV320AIC36IZQE
www.ti.com
SBAS387A – MAY 2009 – REVISED JUNE 2010
6.2.4
Page 0 / Register 3:
Reserved Register
READ/
RESET
BIT
DESCRIPTION
WRITE
VALUE
D7–D0
R
0000 0000
Reserved, Write only default values to this register
6.2.5
Page 0 / Register 4:
Clock Setting Register 1, Multiplexers
READ/
RESET
BIT
DESCRIPTION
WRITE
VALUE
D7–D4
R/W
0000
Select PLL Input Clock
0000: MCLK pin is input to PLL
0001: BCLK pin is input to PLL
0010: GPIO1 pin is input to PLL
0011: GPIO2 pin is input to PLL
0100: DIGMIC_CLK pin is input to PLL
0101: DIGMIC_DATA pin is input to PLL
0110: DSD_CLK pin is input to PLL
0111: DSD_DATA pin is input to PLL
1000: DIN pin is input to PLL
others: Reserved
D3–D0
R/W
0000
Select CODEC_CLKIN
0000: MCLK pin is input to CODEC_CLKIN
0001: BCLK pin is input to CODEC_CLKIN
0010: GPIO1 pin is input to CODEC_CLKIN
0011: GPIO2 pin is input to CODEC_CLKIN
0100: DIGMIC_CLK pin is input to CODEC_CLKIN
0101: DIGMIC_DATA pin is input to CODEC_CLKIN
0110: DSD_CLK pin is input to CODEC_CLKIN
0111: DSD_DATA pin is input to CODEC_CLKIN
1000: DIN pin is input to CODEC_CLKIN
others: Reserved
6.2.6
Page 0 / Register 5:
Clock Setting Register 2, PLL P&R Values
READ/
RESET
BIT
DESCRIPTION
WRITE
VALUE
D7
R/W
0
PLL Power Up
0: PLL is powered down
1: PLL is powered up
D6–D4
R/W
001
PLL divider P Value
000: P=8
001: P=1
010: P=2
…
110: P=6
111: P=7
D3–D0
R/W
0001
PLL divider R Value
000: Reserved, do not use
001: R=1
010: R=2
011: R=3
100: R=4
101…111: Reserved, do not use
Copyright 2009–2010, Texas Instruments Incorporated
REGISTER MAP
79
Product Folder Link(s): TLV320AIC36
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