SBAS387A – MAY 2009 – REVISED JUNE 2010
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1.3
Description
The TLV320AIC36 (sometimes referred to as the AIC36) is a flexible, low-power, low-voltage stereo audio codec
with programmable inputs and outputs, fully programmable miniDSP, fixed predefined and parameterizable signal
processing blocks, integrated PLL, integrated LDOs, and flexible digital interfaces.
1.3.1
Detailed Description
The TLV320AIC36 features two fully programmable miniDSP cores that support application-specific
algorithms in the record and/or the playback path of the device. The miniDSP cores are fully software
controlled.
Extensive Register based control of power, input/output channel configuration, gains, effects,
pin-multiplexing, and clocks is included, allowing the device to be precisely targeted to its application. The
device can cover operations from 8-kHz mono voice playback to audio stereo 192-kHz DAC playback,
making it ideal for portable battery-powered audio and telephony applications.
The record path of the TLV320AIC36 covers operations from 8-kHz mono to 192-kHz stereo recording,
and contains programmable input channel configurations covering single-ended and differential setups, as
well as floating or mixing input signals. It also includes a digitally controlled stereo microphone preamplifier
and integrated microphone bias. Digital signal processing blocks can remove audible noise that may be
introduced by mechanical coupling (for example, optical zooming in a digital camera).
The playback path offers signal-processing blocks for filtering and effects, and supports flexible mixing of
DAC and analog input signals as well as programmable volume controls. The playback path has four
ground-referenced capacitor-free 16
output drivers to support single-ended headphone and receivers.
Two fully differential ground-centered 10K
line output drivers are also available.
An extensive power-management unit with an integral charge pump and three programmable LDOs is
available to create all positive and negative analog supply voltages required by the TLV320AIC36 from a
single positive 2.1-V to 2.8-V supply. Alternatively, the charge pump and LDOs may be individually
bypassed to support a wide variety of power supply configurations.
The required internal clock of the TLV320AIC36 can be derived from multiple sources, including the MCLK
pin, the BCLK pin, the GPIO pin, or the output of the internal PLL, where the input to the PLL again can
be derived from the MCLK pin, the BCLK or GPIO pins. Although using the PLL makes sure that a
suitable clock signal is available, it is not recommended for the lowest power settings. The PLL is highly
programmable and can accept available input clocks in the range of 512 kHz to 50 MHz.
The device is available in the 5-mm × 5-mm, MicroStar Junior 80-VFBGA package.
2
INTRODUCTION
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