參數(shù)資料
型號(hào)： TLV320AIC36IZQE
廠商： TEXAS INSTRUMENTS INC
元件分類： 消費(fèi)家電
英文描述： SPECIALTY CONSUMER CIRCUIT, PBGA80
封裝： 5 X 5 MM, GREEN, PLASTIC, VFBGA-80
文件頁數(shù)： 103/165頁
文件大?。?/td> 1895K
代理商： TLV320AIC36IZQE
SBAS387A – MAY 2009 – REVISED JUNE 2010
www.ti.com
Step 2
Setting up the device through register programming:
The following list gives a sequence of items that must be executed between powering the device up and
reading data from the device:
Define starting point:
Initiate SW Reset
Program PMU Settings: Turn on charge pump
Turn on ADC and DAC LDO with current limit
Program clock setting:s Program PLL clock dividers P, J,D, R (if PLL is necessary)
Power up PLL (if PLL is necessary)
Program and power up NADC
Program and power up MADC
Program OSR value
Program the processing block to be used
Program Codec
Set word length, BCLK, WCLK I/O, mode type, for example I2S/DSP
Interface:
Program Analog Blocks Program common mode voltage
Power up ADC
Program common mode startup sequence
Route inputs/common mode to ADC
Unmute PGA and set gains
Release LDO current limit
Unmute digital volume control
See Section 5.20 for a detailed application example.
5.11 DAC
The TLV320AIC36 includes a stereo audio DAC supporting data rates from 8 to 192kHz. Each channel of
the stereo audio DAC consists of a signal-processing engine with fixed processing blocks, a
programmable miniDSP, a digital interpolation filter, multi-bit digital delta-sigma modulator, and an analog
reconstruction filter. The DAC is designed to provide enhanced performance at low sampling rates through
increased oversampling and image filtering, thereby keeping quantization noise generated within the
delta-sigma modulator and signal images strongly suppressed within the audio band to beyond 20kHz. To
handle multiple input rates and optimize power dissipation and performance, the TLV320AIC36 allows the
system designer to program the oversampling rates over a wide range from 1 to 1024 by configuring the
Page 0, Reg 13, and Reg 14. The system designer can choose higher oversampling ratios for lower input
data rates and lower oversampling ratios for higher input data rates.
The TLV320AIC36 DAC channel includes a built-in digital interpolation filter to generate oversampled data
for the sigma delta modulator. The interpolation filter can be chosen from three different types depending
on required frequency response, group delay and sampling rate.
42
APPLICATION INFORMATION
Copyright 2009–2010, Texas Instruments Incorporated
Product Folder Link(s): TLV320AIC36
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