參數(shù)資料
型號(hào)： TLV320AIC36IZQE
廠商： TEXAS INSTRUMENTS INC
元件分類： 消費(fèi)家電
英文描述： SPECIALTY CONSUMER CIRCUIT, PBGA80
封裝： 5 X 5 MM, GREEN, PLASTIC, VFBGA-80
文件頁數(shù)： 128/165頁
文件大小： 1895K
代理商： TLV320AIC36IZQE
LD(n)
LD(n+1)
WORD
CLOCK
BIT
CLOCK
DATA
-
1
-
2
-
3
2
1
0
3
-
1
-
2
-
3
2
1
0
3
-
1
-
2
N N N
-
3
RD (n)
LEFT CHANNEL
RIGHT CHANNEL
LD(n)=n'thsampleofleftchanneldata
RD(n)=n'thsampleofrightchanneldata
LD(n)
LD (n+1)
WORD
CLOCK
BIT
CLOCK
DATA
-
1
4
3
2
5
1
0
-
1
4
3
2
5
1
0
N
-
1
5
RD(n)
LEFT CHANNEL
RIGHT CHANNEL
LD(n)=n'thsampleofleftchanneldata
RD(n)=n'thsampleofrightchanneldata
LD(n)
LD(n+1)
WORD
CLOCK
BIT
CLOCK
DATA
-
1
-
2
-
3
2
1
0
3
-
1
-
2
-
3
2
1
0
3
-
1
-
2
N N
N
N N
N
N N
N
-
3
RD(n)
LEFT CHANNEL
RIGHT CHANNEL
LD(n)=n'thsampleofleftchanneldata
RD(n)=n'thsampleofrightchanneldata
www.ti.com
SBAS387A – MAY 2009 – REVISED JUNE 2010
Figure 5-39. Timing Diagram for I2S Mode
Figure 5-40. Timing Diagram for I2S Mode With Offset = 2
Figure 5-41. Timing Diagram for I2S Mode With Offset = 0 and Bit Clock Invert
For I2S mode, the number of bit-clocks per channel should be greater than or equal to the programmed
word-length of the data. Also the programmed offset value should be less than the number of bit-clocks
per frame by at least the programmed word-length of the data.
5.17.1.4 DSP Mode
The Audio Interface of the TLV320AIC36 can be put into Right Justified Mode by programming Page 0,
Register 25, D(7:6) = 01. In DSP mode, the falling edge of the word clock starts the data transfer with the
left channel data first and immediately followed by the right channel data. Each data bit is valid on the
falling edge of the bit clock.
Copyright 2009–2010, Texas Instruments Incorporated
APPLICATION INFORMATION
65
Product Folder Link(s): TLV320AIC36
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