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TMXF28155 Super Mapper
155/51 Mbits/s SONET/SDH x28/x21 DS1/E1
Preliminary Data Sheet, Rev. 1
October 2000
106
Lucent Technologies Inc.
TMUX Functional Description
(continued)
Receive Direction (Receive Path from Sonet/SDH)
(continued)
Path Monitoring Functions
The following sections describe the path monitoring functions. For STM-1 signals, the values corresponding to
STS-1 #1 are the relevant signals. For STS-3 input data, there are three versions of each path monitor, one corre-
sponding to each STS-1. The mode bits are applied to the monitors of all three STS-1s.
J1 Monitor.
J1 (path trace) monitoring has six different monitoring modes controlled by TMUX_J1MONMODE[2:0]
(Table 57). The J1 monitoring mode for all three STS-1s within an STS-3 signal is the same.
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TMUX_J1MONMODE[2:0] = 000: The TMUX latches the value of the J1 byte every frame for a total of 64 bytes
in TMUX_J1DMON[1—3][1—64][7:0] (Table 99, Table 100, and Table 101). The TMUX compares the incoming
J1 byte with the next expected value (the expected value is obtained by cycling through the previous stored 64
received bytes in round robin fashion) and setting the path trace identifier state register bit(s), TMUX_RTIMP[1—
3] (Table 54), if different. Any change to the path trace identifier is reported in TMUX_RTIMPD[1—3] (Table 45),
with interrupt mask bits, TMUX_RTIMPM[1—3] (Table 49).
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TMUX_J1MONMODE[2:0] = 001: This is the SONET framing mode. The hardware looks for the 0x0A character
to indicate that the next byte is the first byte of the path trace message. The J1 byte message is continuously
written into registers, TMUX_J1DMON[1—3][1—64][7:0], with the first byte residing at the first address. If any
received byte does not match the previously received byte for its location, then the state bit(s),
TMUX_RTIMP[1—3], is set. Any change to the path trace identifier is reported in TMUX_RTIMPD[1—3], with
interrupt masks bits, TMUX_RTIMPM[1—3].
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TMUX_J1MONMODE[2:0] = 010: This is the SDH framing mode. The hardware looks for the byte with the MSB
set to one, which indicates that the next byte is the second byte of the message. The rest of operation is the
same as in SONET framing mode except that there are 16 bytes instead of 64.
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TMUX_J1MONMODE[2:0] = 011: A new J1 byte (TMUX_J1DMON[1][7:0]) will be detected after a number of
consecutive consistent occurrences of a new pattern (determined by the value in TMUX_CNTDJ1[3:0]
(Table 61)) in the J1 overhead byte. Any changes to this byte must be reported in TMUX_RTIMPD[1—3], with the
interrupt mask bits, TMUX_RTIMPM[1—3]. The delta bit(s) in this mode indicate a change in state for the
TMUX_J1DMON[1][7:0] byte, and the state bits, TMUX_RTIMP[1—3], are not used.
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TMUX_J1MONMODE[1:0] = 100: The user will program the 64 expected values of J1 in
TMUX_EXPJ1DMON[1—3][1—64][7:0] (Table 96, Table 97, and Table 98), in SONET framing mode, where the
first expected byte, the byte following the 0x0A character, is written into the first location of
TMUX_EXPJ1DMON[1][7:0]. The TMUX will compare the incoming J1 sequence with the stored expected value,
setting the path trace identifier state bit(s), TMUX_RTIMP[1—3] if they are different. Any change to the path trace
identifier is reported in TMUX_RTIMPD[1—3], with interrupt mask bits, TMUX_RTIMPM[1—3].
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TMUX_J1MONMODE[1:0] = 101: The user will program the 16 expected values of J1 in EXPJ1DMON[1—
16][7:0] in SDH framing mode, where the first byte of the message has the MSB set to 1. The TMUX compares
the incoming J1 sequence with the stored expected value, setting the state register bit(s), TMUX_RTIMP[1—3], if
they’re different. Any change to path trace identifier is reported in register bits, TMUX_RTIMPD[1—3], with inter-
rupt mask bits, TMUX_RTIMPM[1—3].
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TMUX_J1MONMODE[1:0] = 110 and 111 are currently undefined.