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TMXF28155 Super Mapper
155/51 Mbits/s SONET/SDH x28/x21 DS1/E1
Preliminary Data Sheet, Rev. 1
October2000
206
Lucent Technologies Inc.
SPE Mapper Functional Description
(continued)
PATH Termination Block
(continued)
I
The pointer interpreter transitions out of the INC state based on the following conditions:
— If NDF is enabled on the incoming H1 and H2 bytes, the pointer interpreter transitions from the INC state into
the NDF state.
— Following three consecutive frames with all ones in the H1 and H2 bytes, the pointer interpreter transitions from
the INC state into the AIS-TU3 state.
— Following three new consecutive, consistent, and valid pointers, the pointer interpreter transitions from the INC
state into the NORM state.
— Following any three consecutive, consistent, and valid pointers, the pointer interpreter transitions from the INC
state into the NORM state.
— Following the number of consecutive invalid pointers (determined by the value programmed in
SPE_CNTDLOPCNT[1:0] (Table 125)), the pointer interpreter transitions from the INC state into the LOP-TU3
state.
I
The pointer interpreter transitions into the DEC state based on the following conditions:
— When operating in the 8 of 10 mode (SPE_8ORMAJORITY = 1 (Table 125)), if 8 of the 10 I and D bits are
correct for a pointer decrement on the incoming H1 and H2 bytes, the pointer interpreter transitions into the
DEC state. Otherwise, if 3 of the 5 I bits and 3 of the 5 D bits are correct for a pointer decrement on the incoming
H1 and H2 bytes the pointer interpreter transitions into the DEC state.
I
The pointer interpreter transitions out of the DEC state based on the following conditions:
— If NDF is enabled on the incoming H1 and H2 bytes, the pointer interpreter transitions from the DEC state into
the NDF state.
— Following three consecutive frames with all ones in the H1 and H2 bytes, the pointer interpreter transitions from
the DEC state into the AIS-TU3 state.
— Following three new consecutive, consistent, and valid pointers, the pointer interpreter transitions from the
DEC state into the NORM state.
— Following any three consecutive, consistent, and valid pointers, the pointer interpreter transitions from the DEC
state into the NORM state.
— Following the number of consecutive invalid pointers (determined by the value programmed in
SPE_CNTDLOPCNT[1:0]), the pointer interpreter transitions from the DEC state into the LOP-TU3 state.
I
Pointer increments and decrements will be counted and presented to the microprocessor as follows:
— Pointer increments and decrements will be monitored and counted internally.
— The internal and latched counts will be forced to 0x00 if device pin AUTO_AIS (AC6, AE6, and AD6) = 1 (from
TMUX), bit SPE_RLOP = 1 (Table 124), or bit SPE_RAIS = 1 (Table 124).
— Latched counts, SPE_RPTR_INC[10:0] (Table 137) and SPE_RPTR_DEC[10:0] (Table 137), will be updated
coincident with the end of a performance monitor interval.
— The internal counters will reset to 0x00 coincident with the end of a performance monitor interval.
— If SMPR_SAT_ROLLOVER = 1 (Table 15), the internal running counts will hold at their maximum value. Oth-
erwise, the counts will rollover.
— However, increment and decrement event indications should be ignored during LOP state.
I
LOP-TU3(TU-3 path LOP) and AIS-TU3(TU-3 path AIS) will be detected and reported to the microprocessor.
Both the LOP-TU3 and AIS-TU3 conditions will contribute to the AUTO AIS control signal from the SPE mapper
to the VT mapper. Any change in state of SPE_RLOP (Table 124) or SPE_RAIS (Table 124) will be reported to
the microprocessor via SPE_RLOPD (Table 122) and SPE_RAISD (Table 122). Unless the appropriate mask bit
is set (SPE_RLOPM/SPE_RAISM (Table 123)), SPE_RLOPD = 1 or SPE_RAISD = 1 will generate an interrupt.
I
The current TU-3 pointer value is stored in SPE_STORED_PTR[9:0] (Table 137).